SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

The SYNC/RESET pin on the ADS131M0x

The ADS131M08 provides a SYNC/RESET pin to enable a hardware mechanism that establishes a common time reference across all devices in the system. Simultaneously pulsing the SYNC/RESET low on every ADS131M08 in the system resets each device's internal digital filter, aligning all devices to the SYNC/RESET pulse. In global-chop mode, this synchronization is particularly critical because the device starts conversions immediately upon reset, leaving no delay between the synchronization pulse and the first sample. Synchronization preserves all phase calibration settings, ensuring that previously compensated measurement hardware phase errors (such as those from CTs or amplifiers) remain corrected across all devices. After synchronization, all devices sample their inputs at precisely the same instant, eliminating inter-device phase errors and enabling accurate phase-sensitive measurements. Figure 4-2 shows the signals of two synchronized ADS131M08 devices with no delay between the falling edges.

 DRDY signals between two ADS131M0x with same external clock with synchronizationFigure 4-2 DRDY signals between two ADS131M0x with same external clock with synchronization