Some important considerations apply when using the ADS131M08 phase calibration feature. Applications requiring a negative phase shift can write a negative value to the PHASEn[9:0] bits. However, a negative phase shift requires an additional step of setting the DRDY_SEL[1:0] bits in the MODE register. These bits configure $\overline{\mathrm{D}\mathrm{R}\mathrm{D}\mathrm{Y}}$ to assert based on different channel conditions and availability of conversion data. By default, DRDY_SEL = 00b such that $\overline{\mathrm{D}\mathrm{R}\mathrm{D}\mathrm{Y}}$ asserts when the channel with the largest positive phase calibration setting has a new conversion result. Leaving DRDY_SEL unchanged while writing a negative value to the PHASEn register causes $\overline{\mathrm{D}\mathrm{R}\mathrm{D}\mathrm{Y}}$ to trigger without an offset. Set DRDY_SEL = 10b or 11b to $\overline{\mathrm{D}\mathrm{R}\mathrm{D}\mathrm{Y}}$configure to assert when the channel with the most negative phase calibration setting has new conversion data. Refer to the Data Ready ($\overline{\mathrm{D}\mathrm{R}\mathrm{D}\mathrm{Y}}$) section of the ADS131M08 datasheet for more information on the DRDY_SEL bits.

The phase calibration feature of the ADS131M08 is disabled when global-chop mode is used. Global-chop mode resets the digital filter of the ADC whenever it changes the input polarity, which disables phase calibration. This is explained in the Global-Chop Mode section of the ADS131M08 datasheet.

Phase shifts larger than half the sample period require specific steps for an OSR less than 2048. Refer to the Channel Phase Calibration section of the ADS131M08 datasheet for these steps.