SDAA451 July   2026 ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2What is phase shift and phase error?
  6. 3How to calibrate out phase error with the ADS131M08
    1. 3.1 Determining the phase error
    2. 3.2 Converting to the time domain
    3. 3.3 Converting to modulator clock cycles
    4. 3.4 Converting to binary and writing to the PHASEn[9:0] bits
    5. 3.5 Phase calibration considerations
    6. 3.6 Summarizing the phase calibration process
    7. 3.7 Using the Phase Calibration Feature
      1. 3.7.1 Phase calibration considerations examples
  7. 4Synchronizing the ADS131M0x
    1. 4.1 The SYNC/RESET pin on the ADS131M0x
    2. 4.2 The importance of routing the clock signal
      1. 4.2.1 Single Clock Buffer
      2. 4.2.2 Multiple Clock Buffers
  8. 5Summary
  9. 6References

3 How to calibrate out phase error with the ADS131M08

The ADS131M08 is an 8-channel, 24-bit, simultaneous-sampling delta-sigma ADC. Subsequent sections use the ADS131M08 as an example, but the information applies to any device in the ADS131M0x family. The ADS131M08 provides a built-in feature to compensate for phase errors introduced by external measurement hardware such as CTs. The PHASEn[9:0] bits in the CHn_CFG register implement the phase compensation. Replace the n in PHASEn[9:0] with the specific channel number to apply the phase adjustment to that channel. The remainder of this section describes how to calculate the desired phase shift and write to the PHASEn[9:0] bits in the CHn_CFG register.