SLUS652E March   2005  – April 2020 UCD8220

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 UCD8220 Typical Simplified Push-Pull Converter Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PWP|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP With PowerPAD
Top View
UCD8220 PWP_LUS652.gif
NC – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
3V3 3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place a 0.22-μF ceramic capacitor from this pin to analog ground.
AGND 5 — Analog ground return
CLF 7 O Current-limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output driver is forced low and the current-limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on the CLK pin. This signal is also used for the start-up handshaking between the digital controller and the analog controller
CLK 2 I Clock. Input pulse train contains operating frequency and maximum duty cycle limit. This pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. An internal Schmitt trigger comparator isolates the internal circuitry from any external noise.
CS 9 I Current sense pin. A fast current-limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting.
CTRL 6 I Input for the error feedback voltage from the external error amplifier. This input is multiplied by 0.5 and routed to the negative input of the PWM comparator
ILIM 8 I Current-limit threshold set pin. The current-limit threshold can be set to any value between 0.25 V and 1 V. The default value while open is 0.5 V.
ISET 4 I Pin for programming the current used to set the amount of slope compensation in peak current-mode control or to set the internal capacitor charging in voltage-mode control.
NC 1 — No connection.
15
16
OUT1 12 O The high-current TrueDrive integrated circuit driver output.
OUT2 11 O The high-current TrueDrive integrated circuit driver output.
PGND 10 — Power ground return. This pin should be connected close to the source of the power MOSFET.
PVDD 13 — Supply pin provides power for the output drivers. This pin is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND.
VDD 14 I Supply input pin to power the control circuitry. Bypass the pin with a capacitor with a value of at least 4.7 μF, returned to AGND.