7.3.1 CLK Input Time-Domain Digital Pulse Train

While the loop is closed in the analog domain, the UCD8220 device is managed by a time-domain digital pulse train from a digital controller. The pulse train, shown as CLK in Figure 27, contains the operating frequency and maximum duty-cycle limit and therefore controls the power supply operation as previously listed. The pulse train uses a Texas Instruments communication protocol which is a proprietary communication system that provides control of the power supply operation through software programming. The rising edge of the CLK signal represents the switching frequency. Figure 27 depicts the operation of the UCD8220 device in one of five modes. At the time when the internal signal REF OK is low, the UCD8220 device is not ready to accept CLK inputs. When the REF OK signal goes high, then the device is ready to process inputs. While the CLK input is low, the outputs are disabled and the CLK signal is used as an enable input. When the digital controller completes the initialization routine and verifies that all voltages are within operating range, then the controller begins the soft-start procedure by slowly ramping up the duty cycle of the CLK signal, while maintaining the desired switching frequency. The CLK duty cycle continues to increase until it reaches steady-state where the analog control loop takes over and regulates the output voltage to the desired set point. During steady state, the duty cycle of the CLK pulse can be set using a volt-second product calculation to protect the primary of the power transformer from saturation during transients.

When the power supply detects an overcurrent event, it enters the current-limit mode where the outputs are quickly turned off and the CLF signal is set high to notify the digital controller that the last power pulse was truncated. This technique is beneficial because it allows the digital controller to decide how to handle this overcurrent event while providing some protection to the other components being supplied by this device.

The software is now in charge of the response to overcurrent events. In typical analog designs, the power supply response to overcurrent is hardwired in the silicon. With this method, the user can configure the response differently for different applications. For example, the software can be configured to latch-off the power supply in response the first overcurrent event, or to allow a fixed number of current-limit events, so that the supply is capable of starting up into a capacitive load. The user can also configure the supply to enter into hiccup mode immediately or after a certain number of current-limit events. As described later in this data sheet, the current limit threshold can be varied in time to create unique current limit profiles. For example, the current limit set point can be set high for a predefined number of cycles to blow a manual fuse, and can be reduced down to protect the system in the event of a faulty fuse.

Figure 27. Timing and Circuit Operation Diagram