SLUS652E March 2005 – April 2020 UCD8220
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY SECTION | |||||||
Supply current, OFF | VDD = 4.2 V | 300 | 500 | µA | |||
Supply current, ON | Outputs not switching, CLK = low | 2 | 3 | mA | |||
LOW VOLTAGE UNDERVOLTAGE LOCKOUT | |||||||
VDD UVLO ON | 4.25 | 4.5 | 4.75 | V | |||
VDD UVLO OFF | 4.05 | 4.25 | 4.45 | V | |||
VDD UVLO hysteresis | 150 | 250 | 350 | mV | |||
REFERENCE / EXTERNAL BIAS SUPPLY | |||||||
3V3 initial set point | TA = 25°C, ILOAD = 0 | 3.267 | 3.3 | 3.333 | V | ||
3V3 set point over temperature | 3.234 | 3.3 | 3.366 | V | |||
3V3 load regulation | ILOAD = 1 mA to 10 mA, VDD = 5 V | 1 | 6.6 | mV | |||
3V3 line regulation | VDD = 4.75 V to 12 V, ILOAD = 10 mA | 1 | 6.6 | mV | |||
Short circuit current | VDD = 4.75 to 12 V | 11 | 20 | 35 | mA | ||
3V3 OK threshold, ON | 3.3 V rising | 2.9 | 3.0 | 3.1 | V | ||
3V3 OK threshold, OFF | 3.3 V falling | 2.7 | 2.8 | 2.9 | V | ||
CLOCK INPUT (CLK) | |||||||
VIT+ | HIGH, positive-going input threshold voltage | 1.65 | 2.08 | V | |||
VIT– | LOW negative-going input threshold voltage | 1.16 | 1.5 | V | |||
(VIT+) – (VIT–) | Input voltage hysteresis | 0.6 | 0.8 | V | |||
Frequency | OUTx = 1 MHz | 2 | MHz | ||||
SLOPE COMPENSATION (ISET) | |||||||
ISET Voltage | VISET , 3V3 = 3.3 V, ±2% | 1.78 | 1.84 | 1.90 | V | ||
m | VSLOPE (I-Mode) | RISET = 6.19 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V | 1.48 | 2.12 | 2.76 | V/µs | |
RISET = 100 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V | 0.099 | 0.142 | 0.185 | ||||
RISET = 499 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V | 0.019 | 0.028 | 0.037 | ||||
m | VSLOPE (V-Mode) | RISET = 4.99 kΩ to 3V3, CTRL = 2.5 V | 1.44 | 2.06 | 2.68 | V/µs | |
RISET = 100 kΩ to 3V3, CTRL = 2.5 V | 0.079 | 0.114 | 0.148 | ||||
RISET = 402 kΩ to 3v3, CTRL = 2.5 V | 0.019 | 0.027 | 0.035 | ||||
ISET resistor range | Current mode control; RISET connected to AGND | 6.19 | 499 | kΩ | |||
ISET resistor range | Voltage mode control; RISET connected to 3V3 | 4.99 | 402 | kΩ | |||
ISET current range | Voltage mode control with Feed-Forward; RISET connected to VIN | 3.7 | 300 | μA | |||
PWM | |||||||
PWM offset at CTRL input | 3V3 = 3.3 V ±2% | 0.45 | 0.51 | 0.6 | V | ||
CTRL buffer gain(1) | Gain from CTRL to PWM comparator input | 0.5 | V/V | ||||
CURRENT LIMIT (ILIM) | |||||||
ILIM internal current limit threshold | ILIM = OPEN | 0.466 | 0.5 | 0.536 | V | ||
ILIM maximum current limit threshold | ILIM = 3.3 V | 0.975 | 1.025 | 1.075 | V | ||
ILIM current limit threshold | ILIM = 0.75 V | 0.700 | 0.725 | 0.750 | V | ||
ILIM minimum current limit threshold | ILIM = 0.25 V | 0.2 | 0.23 | 0.25 | V | ||
CLF output high level | CS > ILIM , ILOAD = –7 mA | 2.64 | V | ||||
CLF output low level | CS ≤ ILIM, ILOAD = 7 mA | 0.66 | V | ||||
CURRENT SENSE COMPARATOR | |||||||
Bias voltage | Includes CS comp offset | 5 | 25 | 50 | mV | ||
Input bias current | –1 | μA | |||||
CURRENT SENSE DISCHARGE TRANSISTOR | |||||||
Discharge resistance | CLK = low, resistance from CS to AGND | 10 | 35 | 75 | Ω | ||
OUTPUT DRIVERS | |||||||
Source current(1) | VDD = 12 V, CLK = high, OUTx = 5 V | 4 | A | ||||
Sink current(1) | VDD = 12 V, CLK = low, OUTx = 5 V | 4 | A | ||||
Source current(1) | VDD = 4.75 V, CLK = high, OUTx = 0 | 2 | A | ||||
Sink current(1) | VDD = 4.75 V, CLK = low, OUTx = 4.75 V | 3 | A | ||||
Output with VDD < UVLO | VDD = 1.0 V, ISINK = 10 mA | 0.8 | 1.2 | V |