ZHCSMR1C october   2019  – september 2021 UCC5870-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Electrical Characteristics
    8. 6.8  SPI Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
        1. 7.3.1.1 VCC1
        2. 7.3.1.2 VCC2
        3. 7.3.1.3 VEE2
        4. 7.3.1.4 VREG1
        5. 7.3.1.5 VREG2
        6. 7.3.1.6 VREF
        7. 7.3.1.7 Other Internal Rails
      2. 7.3.2 Driver Stage
      3. 7.3.3 Integrated ADC for Front-End Analog (FEA) Signal Processing
        1. 7.3.3.1 AI* Setup
        2. 7.3.3.2 ADC Setup and Sampling Modes
          1. 7.3.3.2.1 Center Sampling Mode
          2. 7.3.3.2.2 Edge Sampling Mode
          3. 7.3.3.2.3 Hybrid Mode
        3. 7.3.3.3 DOUT Functionality
      4. 7.3.4 Fault and Warning Classification
      5. 7.3.5 Diagnostic Features
        1. 7.3.5.1  Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
          1. 7.3.5.1.1 Built-In Self Test (BIST)
            1. 7.3.5.1.1.1 Analog Built-In Self Test (ABIST)
            2. 7.3.5.1.1.2 Function BIST
            3. 7.3.5.1.1.3 Clock Monitor
              1. 7.3.5.1.1.3.1 Clock Monitor Built-In Self Test
        2. 7.3.5.2  CLAMP, OUTH, and OUTL Clamping Circuits
        3. 7.3.5.3  Active Miller Clamp
        4. 7.3.5.4  DESAT based Short Circuit Protection (DESAT)
        5. 7.3.5.5  Shunt Resistor based Overcurrent Protection (OCP) and Short Circuit Protection (SCP)
        6. 7.3.5.6  Temperature Monitoring and Protection for the Power Transistors
        7. 7.3.5.7  Active High Voltage Clamping (VCECLP)
        8. 7.3.5.8  Two-Level Turn-Off
        9. 7.3.5.9  Soft Turn-Off (STO)
        10. 7.3.5.10 Thermal Shutdown (TSD) and Temperature Warning (TWN) of Driver IC
        11. 7.3.5.11 Active Short Circuit Support (ASC)
        12. 7.3.5.12 Shoot-Through Protection (STP)
        13. 7.3.5.13 Gate Voltage Monitoring and Status Feedback
        14. 7.3.5.14 VGTH Monitor
        15. 7.3.5.15 Cyclic Redundancy Check (CRC)
          1. 7.3.5.15.1 Calculating CRC
        16. 7.3.5.16 Configuration Data CRC
        17. 7.3.5.17 SPI Transfer Write/Read CRC
          1. 7.3.5.17.1 SDI CRC Check
          2. 7.3.5.17.2 SDO CRC Check
        18. 7.3.5.18 TRIM CRC Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 State 1: RESET
      2. 7.4.2 State 2: Configuration 1
      3. 7.4.3 State 3: Configuration 2
      4. 7.4.4 State 4: Active
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 System Configuration of SPI Communication
          1. 7.5.1.1.1 Independent Slave Configuration
          2. 7.5.1.1.2 Daisy Chain Configuration
          3. 7.5.1.1.3 Address-based Configuration
        2. 7.5.1.2 SPI Data Frame
          1. 7.5.1.2.1 Writing a Register
          2. 7.5.1.2.2 Reading a Register
    6. 7.6 Register Maps
      1. 7.6.1 UCC5870 Registers
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Dissipation Considerations
      2. 8.1.2 Device Addressing
    2. 8.2 Typical Application Using Internal ADC Reference and Power FET Sense Current Monitoring
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC1, VCC2, and VEE2 Bypass Capacitors
        2. 8.2.2.2 VREF, VREG1, and VREG2 Bypass Capacitors
        3. 8.2.2.3 Bootstrap Capacitor (VBST)
        4. 8.2.2.4 VCECLP Input
        5. 8.2.2.5 External CLAMP Output
        6. 8.2.2.6 AI* Inputs
        7. 8.2.2.7 OUTH/ OUTL Outputs
        8. 8.2.2.8 nFLT* Outputs
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application Using DESAT Power FET Monitoring
      1. 8.3.1 Detailed Design Procedure
        1. 8.3.1.1 DESAT Input
      2. 8.3.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC1 Power Supply
    2. 9.2 VCC2 Power Supply
    3. 9.3 VEE2 Power Supply
    4. 9.4 VREF Supply (Optional)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.6.1 UCC5870 Registers

Table 7-4 lists the memory-mapped registers for the device registers. All register offset addresses not listed in Table 7-4 should be considered as reserved locations and the register contents should not be modified.

Table 7-4 UCC5870 Registers
Offset Acronym Register Name: description SPI write access enabled state Section Covered by Configuration Data CRC?
0x0 CFG1 Configuration register 1: Primary side device configuration. VCC1 UVLO and OVLO, IO deglitch timer, Over temperature, nFLT2 pin function, and dead time setting. Configuration 2 Go Yes
0x1 CFG2 Configuration register 2: nFLT1,2 pin function setting. Configuration 2 Go Yes
0x2 CFG3 Configuration register 3: Gate driver output fault reaction setting Configuration 2 Go Yes
0x3 CFG4 Configuration register 4: Protection and monitoring function setting. Enabling or disabling of the functions. Configuration 2 Go Yes
0x4 CFG5 Configuration register 5: Protection and monitoring function setting. Enabling or disabling of the functions. Threshold setting. Configuration 2 Go Yes
0x5 CFG6 Configuration Registers 6: Protection and monitoring function setting. Enabling or disabling of the functions. Threshold and timer setting. Configuration 2 Go Yes
0x6 CFG7 Configuration Registers 7: Protection and monitoring function setting. Enabling or disabling of the functions. Threshold and timer setting. Configuration 2 Go Yes
0x7 CFG8 Configuration register 8: Protection and monitoring function setting. Enabling or disabling of the functions. Threshold and timer setting. Bit15-7,5-3: Configuration 2;Bit6,2-0,: Configuration 2; Active Go Yes
0x8 CFG9 Configuration register 9: nFLT1,2 pin function setting. Configuration 2 Go Yes
0x9 CFG10 Configuration register 10: Gate driver output fault reaction setting. Configuration 2 Go Yes
0xA CFG11 Configuration register 11: Gate driver output fault reaction setting Configuration 2 Go Yes
0xB ADCDATA1 ADC data register 1: Digital representation of sampled AI1 voltage Go No
0xC ADCDATA2 ADC data register 2: Digital representation of sampled AI3 voltage Go No
0xD ADCDATA3 ADC data register 3: Digital representation of sampled AI5 voltage Go No
0xE ADCDATA4 ADC data register 4: Digital representation of sampled AI2 voltage Go No
0xF ADCDATA5 ADC data register 5: Digital representation of sampled AI4 voltage Go No
0x10 ADCDATA6 ADC data register 6: Digital representation of sampled AI6 voltage Go No
0x11 ADCDATA7 ADC data register 7: Digital representation of sampled internal die temperature Go No
0x12 ADCDATA8 ADC data register 8: Digital representation of sampled divided OUTH voltage for VGTH monitor Go No
0x13 CRCDATA SPI CRC Data Register Configuration 2 Go Yes
0x14 SPITEST SPI read/write test Register Configuration 2, Active Go Yes
0x15 GDADDRESS Driver address register Configuration 1 Go Yes
0x16 STATUS1 Status register 1: Fault status. Go No
0x17 STATUS2 Status register 2: Fault and pin status. Go No
0x18 STATUS3 Status register 3: Fault status. Go No
0x19 STATUS4 Status register 4: Fault status. Go No
0x1A STATUS5 Status register 5: Fault status. Go No
0x1B CONTROL1 Control register 1: Diagnostic commands. Configuration 2, Active Go Yes
0x1C CONTROL2 Control register 2: Diagnostic commands. Configuration 2, Active Go Yes
0x1D ADCCFG ADC setting Configuration 2 Go Yes
0x1E DOUTCFG DOUT function setting Configuration 2 Go Yes

Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for access types in this section.

Table 7-5 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.6.1.1 CFG1 Register

CFG1 is shown in Figure 7-45 and described in Table 7-6.

Return to Summary Table.

Figure 7-45 CFG1 Register
15 14 13 12 11 10 9 8
UV1_DIS UVLO1_LEVEL OVLO1_LEVEL IO_DEGLITCH GD_TWN_PRI_EN Reserved OV1_DIS
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x1 R/W-0x1 R/W-0x0 RW-0x0
7 6 5 4 3 2 1 0
RESERVED NFLT2_DOUT_MUX TDEAD
RW-0x0 R/W-0x0 R/W-0x0
Table 7-6 CFG1 Register Field Descriptions
Bit Field Type Reset Description
15 UV1_DIS R/W 0x0

VCC1 UVLO disable:

0x0 = Enabled

0x1 = Disabled
14 UVLO1_LEVEL R/W 0x0

VCC1 UVLO setting:

0x0 = 2.45V (3.3V logic rail)

0x1 = 4.35V (5V logic rail)
13 OVLO1_LEVEL R/W 0x0

VCC1 OVLO setting:

0x0 = 5.65V (5V logic rail)

0x1 = 4.15V (3.3V logic rail)
12-11 IO_DEGLITCH R/W 0x1

IO deglitch (INP and INN) filter time:

0x0 = Deglitch filter bypassed

0x1 = 70ns setting

0x2 = 140ns setting

0x3 = 210ns setting
10 GD_TWN_PRI_DIS R/W 0x1

Over temperature warning of gate driver VCC1 side enable:

0x0 = Enabled

0x1 = Disabled
9 RESERVED R/W 0x0

This bit field is reserved.
8 OV1_DIS R/W 0x0

VCC1 OVLO disable:

0x0 = Enabled

0x1 = Disabled
7 RESERVED R/W 0x0

This bit field is reserved.
6 NFLT2_DOUT_MUX R/W 0x0

nFLT2/DOUT pin function selection:

0x0 = nFLT2

0x1 = DOUT. When this setting is selected, all warnings selected to output to nFLT2 are output on nFLT1.
5-0 TDEAD R/W 0x0

Shoot-through protection dead time:

0x0 = No added deadtime (Interlock function enabled)

0x1 - 0x3F = 105ns to 4445ns with 70ns resolution

Deadtime = code(decimal) x 70ns + 105ns

7.6.1.2 CFG2 Register

CFG2 is shown in Figure 7-46 and described in Table 7-7.

Return to Summary Table.

Figure 7-46 CFG2 Register
15 14 13 12 11 10 9 8
INT_COMM_PRI_FAULT_P OVLO1_FAULT_P UVLO1_FAULT_P STP_FAULT_P CLK_MON_PRI_FAULT_P SPI_FAULT_P CFG_CRC_PRI_FAULT_P
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x1 R/W-0x0
7 6 5 4 3 2 1 0
INT_REG_PRI_FAULT_P TRIM_CRC_PRI_FAULT _P BIST_PRI_FAULT_P RESERVED RESERVED GD_TWN_PRI_FAULT_P VREG1_ILIMIT_FAULT_P PWM_CHK_FAULT_P
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 RW-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-7 CFG2 Register Field Descriptions
Bit Field Type Reset Description
15 INT_COMM_PRI_FAULT_P R/W 0x0

Report inter-die communication failure to nFLT1 output:

0x0 = No

0x1 = Yes
14 OVLO1_FAULT_P R/W 0x0

Report VCC1 OVLO fault to nFLT1 output:

0x0 = Yes

0x1 = No
13 UVLO1_FAULT_P R/W 0x0

Report VCC1 UVLO fault to nFLT1 output:

0x0 = Yes

0x1 = No
12 STP_FAULT_P R/W 0x0

Report STP fault to nFLT1 output:

0x0 = Yes

0x1 = No
11 CLK_MON_PRI_FAULT_P R/W 0x0

Report clock monitor fault to nFLT1 output:

0x0 = Yes

0x1 = No
10-9 SPI_FAULT_P R/W 0x1

Report SPI fault to nFLT* outputs:

0x0 = nFLT1

0x1 = nFLT2

0x2 = No report

0x3 = RESERVED
8 CFG_CRC_PRI_FAULT_P R/W 0x0

Report configuration register CRC fault to nFLT1 output:

0x0 = Yes

0x1 = No
7 INT_REG_PRI_FAULT_P R/W 0x0

Report internal regulator fault to nFLT1 output:

0x0 = Yes

0x1 = No
6 TRIM_CRC_PRI_FAULT_P R/W 0x0

Report TRIM CRC fault to nFLT* outputs:

0x0 = Yes

0x1 = No
5 BIST_PRI_FAULT_P R/W 0x0

Report analog BIST fault to nFLT* outputs:

0x0 = Yes

0x1 = No
4-3 RESERVED R/W 0x0 These bits are reserved. Writing to these bits sets the CFG_CRC_PRI_FAULT.
2 GD_TWN_PRI_FAULT_P R/W 0x0 Report gate driver temp warning to nFLT* outputs:

0x0 = No

0x1 = Yes
1 VREG1_ILIMIT_FAULT_P R/W 0x0

Report VREG1 ILIMIT fault to nFLT1 output:

0x0 = Yes

0x1 = No
0 PWM_CHK_FAULT_P R/W 0x0

Report PWM check fault to nFLT1 output:

0x0 = Yes

0x1 = No

7.6.1.3 CFG3 Register

CFG3 is shown in Figure 7-47 and described in Table 7-8.

Return to Summary Table.

Figure 7-47 CFG3 Register
15 14 13 12 11 10 9 8
FS_STATE_UVLO1_FAULT FS_STATE_OVLO1_FAULT FS_STATE_PWM_CHK FS_STATE_STP_FAULT Reserved FS_STATE_SPI_FAULT
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x2
7 6 5 4 3 2 1 0
FS_STATE_INT_REG_PRI_FAULT FS_STATE_INT_COMM_PRI_FAULT ITO1_EN ITO2_EN FS_STATE_CFG_CRC_PRI_FAULT AI_IZTC_SEL
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-8 CFG3 Register Field Descriptions
Bit Field Type Reset Description
15 FS_STATE_UVLO1_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked VCC1 UVLO fault:

0x0 = Pulled low

0x1 = No action
14 FS_STATE_OVLO1_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked VCC1 OVLO fault:

0x0 = Pulled low

0x1 = No action
13 FS_STATE_PWM_CHK R/W 0x0

OUTH/OUTL output state during an unmasked PWM check fault:

0x0 = Pulled low

0x1 = No action
12-11 FS_STATE_STP_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked shoot-through fault:

0x0 = Low

0x1 = High

0x2 = Reserved

0x3 = No action
10 RESERVED R/W 0x0

Reserved. Writing to these bits sets the CFG_CRC_PRI_FAULT.
9-8 FS_STATE_SPI_FAULT R/W 0x2

OUTH/OUTL output state during an unmasked SPI communication fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = No action

0x3 = No action
7 FS_STATE_INT_REG_PRI_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked internal regulator fault:

0x0 = Pulled low

0x1 = No action
6 FS_STATE_INT_COMM_PRI_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked internal communication result:

0x0 = Pulled low

0x1 = No action
5 ITO1_EN R/W 0x0

Current source output at AI1, AI3, and AI5:

0x0 = Disabled

0x1 = Enabled
4 ITO2_EN R/W 0x0

Current source output at AI2, AI4, and AI6:

0x0 = Disabled

0x1 = Enabled
3 FS_STATE_CFG_CRC_PRI_FAULT R/W 0x0

Default OUTH/OUTL output state in case of configuration register CRC fault:

0x0 = Pulled low

0x1 = No action
2-0 AI_IZTC_SEL R/W 0x0

AI1, AI3, AI5 bias current enable. Additionally, ITO1_EN must be set to '1'.:

0x0 = All bias current is OFF

0x1 = AI1 bias current is ON

0x2 = AI3 bias current is ON

0x3 = AI1 and AI3 bias current is ON

0x4 = AI5 bias current is ON

0x5 = AI1 and AI5 bias current is ON

0x6 = AI3 and AI5 bias current is ON

0x7 = All bias current is ON

7.6.1.4 CFG4 Register

CFG4 is shown in Figure 7-48 and described in Table 7-9.

Return to Summary Table.

Figure 7-48 CFG4 Register
15 14 13 12 11 10 9 8
UV2_DIS PS_TSD_DEGLITCH DESAT_DEGLITCH OV2_DIS MCLP_CFG GM_BLK
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x1 R/W-0x0 R/W-0x1
7 6 5 4 3 2 1 0
GM_DIS MCLP_DIS VCECLP_EN DESAT_EN SCP_DIS OCP_DIS PS_TSD_EN UVOV3_EN
R/W-0x0 R/W-0x0 R/W-0x1 R/W-0x1 R/W-0x0 R/W-0x1 R/W-0x0 R/W-0x0
Table 7-9 CFG4 Register Field Descriptions
Bit Field Type Reset Description
15 UV2_DIS R/W 0x0

VCC2 UVLO function disable:

0x0 = Enabled

0x1 = Disabled
14-13 PS_TSD_DEGLITCH R/W 0x0

Power switch thermal shutdown (TSD) deglitch filter time:

0x0 = 250ns

0x1 = 500ns

0x2 = 750ns

0x3 = 1000ns
12 DESAT_DEGLITCH R/W 0x0

DESAT deglitch timer option:

0x0 = 158ns

0x1 = 316ns
11 OV2_DIS R/W 0x1

VCC2 OVLO function disable:

0x0 = Enabled

0x1 = Disabled
10 MCLP_CFG R/W 0x0

Active Miller clamp option:

0x0 = Internal

0x1 = External
9-8 GM_BLK R/W 0x1

Gate voltage monitor blanking time:

0x0 = 500ns

0x1 = 1000ns

0x2 = 2500ns

0x3 = 4000ns
7 GM_DIS R/W 0x0

Gate voltage monitor function enable:

0x0 = Enabled

0x1 = Disabled
6 MCLP_DIS R/W 0x0

Active Miller clamp enable:

0x0 = Enabled

0x1 = Disabled
5 VCECLP_EN R/W 0x1

VCE clamp enable:

0x0 = Disabled

0x1 = Enabled
4 DESAT_EN R/W 0x1

DESAT detection enable:

0x0 = Disabled

0x1 = Enabled
3 SCP_DIS R/W 0x0

Short circuit protection (SCP) enable:

0x0 = Enabled

0x1 = Disabled
2 OCP_DIS R/W 0x1

Overcurrent protection (OCP) enable:

0x0 = Enabled

0x1 = Disabled
1 PS_TSD_EN R/W 0x0

Thermal shutdown protection for IGBT enable:

0x0 = Disabled

0x1 = Enabled
0 UVOV3_EN R/W 0x0

VEE2 UVLO and OVLO function enable:

0x0 = Disabled

0x1 = Enabled

7.6.1.5 CFG5 Register

CFG5 is shown in Figure 7-49 and described in Table 7-10.

Return to Summary Table.

Figure 7-49 CFG5 Register
15 14 13 12 11 10 9 8
GM_STO2LTO_DIS DESATTH DESAT_CHG_CURR DESAT_DCHG_EN
RW-0x0 R/W-0xE R/W-0x3 R/W-0x1
7 6 5 4 3 2 1 0
MCLPTH STO_CURR 2LTOFF_STO_EN PWM_MUTE_EN
R/W-0x1 R/W-0x0 RW-0x0 R/W-0x1
Table 7-10 CFG5 Register Field Descriptions
Bit Field Type Reset Description
15 GM_STO2LTO_DIS R/W 0x0

Disable gate monitor fault detection during STO or 2LTOFF:

0x0 = Gate monitor is enabled during STO or 2LTOFF

0x1 = Gate monitor is disabled during STO or 2LTOFF
14-11 DESATTH R/W 0xE

DESAT detection threshold value. DESATTH is programmable from 2.5V to 10V with a 500mV resolution. Calculate DESAT with the following equation:

VDESAT = 2.5V + CodeDESATTH(in decimal)* 500mV

10-9 DESAT_CHG_CURR R/W 0x3

Blanking cap charging current:

0x0 = 0.6mA

0x1 = 0.7mA

0x2 = 0.8mA

0x3 = 1mA
8 DESAT_DCHG_EN R/W 0x1

DESAT input pull down current enable:

0x0 = disabled

0x1 = enabled
7-6 MCLPTH R/W 0x1

Active Miller clamp threshold voltage:

0x0 = 1.5V

0x1 = 2V

0x2 = 3V

0x3 = 4V
5-4 STO_CURR R/W 0x0

Soft turn-off current:

0x0 = 0.3A

0x1 = 0.6A

0x2 = 0.9A

0x3 = 1.2A
3-1 2LTOFF_STO_EN R/W 0x0

STO/2LTOFF is enabled for:

0x0 = Disabled

0x1 = STO for SC and DESAT

0x2 = STO for SC, DESAT, and OC faults

0x3 = STO for SC, DESAT, OC, and PS_TSD faults

0x4 = Disabled

0x5 = 2LTOFF for SC and DESAT

0x6 = 2LTOFF for SC, DESAT, and OC faults

0x7 = 2LTOFF for SC, DESAT, OC, and PS_TSD faults
0 PWM_MUTE_EN R/W 0x1

Mute PWM signal in case of SC/OC/OT faults:

0x0 = Muting is Disabled

0x1 = PWM is muted for tMUTE

7.6.1.6 CFG6 Register

CFG6 is shown in Figure 7-50 and described in Table 7-11.

Return to Summary Table.

Figure 7-50 CFG6 Register
15 14 13 12 11 10 9 8
OCTH SCTH TEMP_CURR
R/W-0x0 R/W-0x2 R/W-0x1
7 6 5 4 3 2 1 0
SC_BLK OC_BLK PS_TSDTH
R/W-0x0 R/W-0x0 R/W-0x2
Table 7-11 CFG6 Register Field Descriptions
Bit Field Type Reset Description
15-12 OCTH R/W 0x0

Overcurrent detection threshold value:

0x0 = 200mV

0x1 = 250mV

0x2 = 300mV

0x3 = 350mV

0x4 = 400mV

0x5 = 450mV

0xF = 950mV
11-10 SCTH R/W 0x2

Short-circuit fault detection threshold value:

0x0 = 500mV

0x1 = 750mV

0x2 = 1000mV

0x3 = 1250mV
9-8 TEMP_CURR R/W 0x1

Constant current source for temp sensing diodes:

0x0 = 0.1mA

0x1 = 0.3mA

0x2 = 0.6mA

0x3 = 1.0mA
7-6 SC_BLK R/W 0x0

Short-circuit detection blanking time:

0x0 = 100ns

0x1 = 200ns

0x2 = 400ns

0x3 = 800ns
5-3 OC_BLK R/W 0x0

Over-current detection blanking time:

0x0 = 500ns

0x1 = 1000ns

0x2 = 1500ns

0x3 = 2000ns

0x4 = 2500ns

0x5 = 3000ns

0x6 = 5000ns

0x7 = 10000ns
2-0 PS_TSDTH R/W 0x2

Power switch thermal shutdown threshold:

0x0 = 1.00V

0x1 = 1.25V

0x2 = 1.50V

0x3 = 1.75V

0x4 = 2.00V

0x5 = 2.25V

0x6 = 2.50V

0x7 = 2.75V

7.6.1.7 CFG7 Register

CFG7 is shown in Figure 7-51 and described in Table 7-12.

Return to Summary Table.

Figure 7-51 CFG7 Register
15 14 13 12 11 10 9 8
UVLO2TH OVLO2TH UVLO3TH OVLO3TH
R/W-0x2 R/W-0x2 R/W-0x2 R/W-0x2
7 6 5 4 3 2 1 0
ADC_EN ADC_SAMP_MODE ADC_SAMP_DLY ADC_FAULT_P FS_STATE_ADC_FAULT
R/W-0x1 R/W-0x0 R/W-0x2 R/W-0x0 R/W-0x0
Table 7-12 CFG7 Register Field Descriptions
Bit Field Type Reset Description
15-14 UVLO2TH R/W 0x2

VCC2 UVLO threshold:

0x0 = 16V (turnon), 15V(turnoff)

0x1 = 14V (turnon), 13V(turnoff)

0x2 = 12V (turnon), 11V(turnoff)

0x3 = 10V (turnon), 9V(turnoff)
13-12 OVLO2TH R/W 0x2

VCC2 OVLO threshold:

0x0 = 23V (turnon), 24V(turnoff)

0x1 = 21V (turnon), 22V(turnoff)

0x2 = 19V (turnon), 20V(turnoff)

0x3 = 17V (turnon), 18V(turnoff)
11-10 UVLO3TH R/W 0x2

VEE2 UVLO threshold:

0x0 = -3V (turnon), -2V (turnoff)

0x1 = -5V (turnon), -4V (turnoff)

0x2 = -8V (turnon), -7V (turnoff)

0x3 = -10V (turnon), -9V (turnoff)
9-8 OVLO3TH R/W 0x2

VEE2 OVLO threshold:

0x0 = -5V (turnon), -6V(turnoff)

0x1 = -7V (turnon), -8V(turnoff)

0x2 = -10V (turnon), -11V(turnoff)

0x3 = -12V (turnon), -13V(turnoff)
7 ADC_EN R/W 0x1

ADC sampling enable:

0x0 = Disabled

0x1 = Enabled
6-5 ADC_SAMP_MODE R/W 0x0

ADC sampling mode:

0x0 = center aligned

0x1 = edge aligned

0x2 = center hybrid mode

0x3 = RESERVED
4-3 ADC_SAMP_DLY R/W 0x2

ADC sampling point minimum delay setting with reference to PWM rising edge:

0x0 = 280ns

0x1 = 560ns

0x2 = 840ns

0x3 = 1120ns

2 ADC_FAULT_P R/W 0x0

Report ADC fault to nFLT1 output:

0x0 = Disabled

0x1 = Enabled
1-0 FS_STATE_ADC_FAULT R/W 0x0

OUTH/OUTL output state during an unmasked ADC fault (VREF OV/UV, VREF ILIM, or ADC buffer overrun):

0x0 = Pulled low

0x1 = Pulled high

0x2 = Hi-Z

0x3 = No action

7.6.1.8 CFG8 Register

CFG8 is shown in Figure 7-52 and described in Table 7-13.

Return to Summary Table.

Figure 7-52 CFG8 Register
15 14 13 12 11 10 9 8
GD_2LOFF_VOLT GD_2LOFF_TIME GD_2LOFF_CURR
R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RESERVED CRC_DIS GD_2LOFF_STO_EN VREF_SEL AI_ASC_MUX IOUT_SEL
RW-0x0 R-0x0 R/W-0x1 R/W-0x1 R/W-0x0 R-0x0
Table 7-13 CFG8 Register Field Descriptions
Bit Field Type Reset Description
15-13 GD_2LOFF_VOLT R/W 0x0

Plateau voltage during two-level turnoff:

0x0 = 6V

0x1 = 7V

0x2 = 8V

0x3 = 9V

0x4 = 10V

0x5 = 11V

0x6 = 12V

0x7 = 13V
12-10 GD_2LOFF_TIME R/W 0x0

Duration of plateau voltage during two-level turnoff:

0x0 = 150ns

0x1 = 300ns

0x2 = 450ns

0x3 = 600ns

0x4 = 1000ns

0x5 = 1500ns

0x6 = 2000ns

0x7 = 2500ns
9-8 GD_2LOFF_CURR R/W 0x0

Gate discharge current for transition to plateau voltage level:

0x0 = 0.3A

0x1 = 0.6A

0x2 = 0.9A

0x3 = 1.2A
7 RESERVED R/W 0x0

This bit field is reserved. Writing to these bits sets the CFG_CRC_SEC_FAULT.
6 CRC_DIS R/W 0x0

Disable configuration CRC check:

0x0 = Enable

0x1 = Disable
5 GD_2LOFF_STO_EN R/W 0x1

STO is enabled for the transition from mid voltage level:

0x0 = Disable

0x1 = Enable
4 VREF_SEL R/W 0x1

Selection of VREF voltage:

0x0 = Internal

0x1 = External
3 AI_ASC_MUX R/W 0x0

AI5/ AI6 function selection:

0x0 = AI5 and AI6 is configured as ASC_EN and ASC input respectively. Current source pull up on AI5 is always off.

0x1 = AI5 and AI6 are configured as ADC inputs. The secondary side ASC function is disabled.
2-0 IOUT_SEL R/W 0x0

Gate drive strength selection. IOUT_SEL may be changed while in ACTIVE mode, however the configuration CRC check must be disabled first by setting CRC_DIS=1 to avoid a configuration CRC fault

0x0 = Gate drive output stage all segments enabled

0x1 =Gate drive output stage 1/3 of segments enabled

0x2 = Gate drive output stage 1/6 of segments enabled

0x3 = Gate drive output stage 1/6 of segments enabled

0x4 = Gate drive output stage 1/6 of segments enabled

0x5 = Gate drive output stage 1/6 of segments enabled

0x6 = Gate drive output stage 1/6 of segments enabled

0x7 = Gate drive output stage 1/6 of segments enabled

7.6.1.9 CFG9 Register

CFG9 is shown in Figure 7-53 and described in Table 7-14.

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Figure 7-53 CFG9 Register
15 14 13 12 11 10 9 8
SPARE SC_FAULT_P OC_FAULT_P GM_FAULT_P UVLO23_FAULT_P OVLO23_FAULT_P PS_TSD_FAULT_P
R/W-0x1 R/W-0x0 R/W-0x0 R/W-0x1 R/W-0x0 R/W-0x0 R/W-0x1
7 6 5 4 3 2 1 0
GD_TSD_FAULT_P INT_COMM_SEC_FAULT_P CFG_CRC_SEC_FAULT_P TRIM_CRC_SEC_FAULT_P INT_REG_SEC_FAULT_P BIST_SEC_FAULT_P VREG2_ILIMIT_FAULT_P CLK_MON_SEC_FAULT_P
R/W-0x0 R/W-0x1 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-14 CFG9 Register Field Descriptions
Bit Field Type Reset Description
15 SPARE R/W 0x1

This bit field has no effect on the driver functionality. It is covered by the CFG_CRC_SEC and does not cause a CRC automatically when written..
14 SC_FAULT_P R/W 0x0

Report SC fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
13 OC_FAULT_P R/W 0x0

Report OC fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
12-11 GM_FAULT_P R/W 0x1

Report gate voltage monitor fault:

0x0 = No (fault masked)

0x1 = nFLT1

0x2 = nFLT2

0x3 = Indicate gate voltage state on nFLT2
10 UVLO23_FAULT_P R/W 0x0

Report VCC2 and VEE2 UVLO faults to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
9 OVLO23_FAULT_P R/W 0x0

Report VCC2 and VEE2 OVLO faults to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
8 PS_TSD_FAULT_P R/W 0x1

Report power switch TSD fault to nFLT1 output:

0x0 = No (fault masked)

0x1 = Yes
7 GD_TSD_SEC_FAULT_P R/W 0x0

Report gate driver TSD fault to nFLT1 output. The thermal shutdown shuts down the secondary side, regardless of the state of this bit:

0x0 = Yes

0x1 = No
6 INT_COMM_SEC_FAULT_P R/W 0x1

Report internal communication fault to nFLT1 output:

0x0 = No (fault masked)

0x1 = Yes
5 CFG_CRC_SEC_FAULT_P R/W 0x0

Report configuration register CRC fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
4 TRIM_CRC_SEC_FAULT_P R/W 0x0

Report TRIM CRC fault to nFLT* output:

0x0 = Yes

0x1 = No (fault masked)
3 INT_REG_SEC_FAULT_P R/W 0x0

Report internal regulator fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
2 BIST_SEC_FAULT_P R/W 0x0

Report ABIST fault to nFLT1 and 2 output:

0x0 = Yes

0x1 = No (fault masked)
1 VREG2_ILIMIT_FAULT_P R/W 0x0

Report VREG2 ILIMIT fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)
0 CLK_MON_SEC_FAULT_P R/W 0x0

Report clock monitor fault to nFLT1 output:

0x0 = Yes

0x1 = No (fault masked)

7.6.1.10 CFG10 Register

CFG10 is shown in Figure 7-54 and described in Table 7-15.

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Figure 7-54 CFG10 Register
15 14 13 12 11 10 9 8
GD_TWN_SEC_EN SPARE FS_STATE_DESAT_SCP FS_STATE_INT_REG_FAULT RESERVED FS_STATE_OCP
R/W-0x1 R/W-0x1 R/W-0x0 R/W-0x0 RW-0x0 R/W-0x0
7 6 5 4 3 2 1 0
FS_STATE_PS_TSD SPARE FS_STATE_GM FS_STATE_INT_COMM_SEC
R/W-0x0 R/W-0x0 R/W-0x2 R/W-0x0
Table 7-15 CFG10 Register Field Descriptions
Bit Field Type Reset Description
15 GD_TWN_SEC_EN R/W 0x1

Over temperature warning of gate driver VCC2 side enable:

0x0 = Disabled

0x1 = Enabled
14 SPARE R/W 0x1

This bit field has no effect on the driver functionality. It is covered by the CFG_CRC_SEC and does not cause a CRC automatically when written.
13-12 FS_STATE_DESAT_SCP R/W 0x0

Default OUTH/OUTL output state in case of DESAT/SCP fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = Reserved

0x3 = No action
11 FS_STATE_INT_REG_FAULT R/W 0x0

Default OUTH/OUTL output state in case of internal regulator fault:

0x0 = Pulled low

0x1 = No action
10 RESERVED R/W 0x0

This bit field is reserved. Writing to these bits sets the CFG_CRC_SEC_FAULT.
9-8 FS_STATE_OCP R/W 0x0

Default OUTH/OUTL output state in case of OC fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = Reserved

0x3 = No action
7-6 FS_STATE_PS_TSD R/W 0x0

Default state in case of IGBT OT fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = Reserved

0x3 = No action
5-4 SPARE R/W 0x0

This bit field has no effect on the driver functionality. It is covered by the CFG_CRC_SEC and does not cause a CRC automatically when written.
3-2 FS_STATE_GM R/W 0x2

Default state in case of gate monitor fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = Hi-Z

0x3 = No action
1-0 FS_STATE_INT_COMM_SEC R/W 0x0

Default state in case of internal communication fault:

0x0 = Pulled low

0x1 = Pulled high

0x2 = Reserved

0x3 = No action

7.6.1.11 CFG11 Register

CFG11 is shown in Figure 7-55 and described in Table 7-16.

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Figure 7-55 CFG11 Register
15 14 13 12 11 10 9 8
FS_STATE_UVLO2 FS_STATE_OVLO2 FS_STATE_UVLO3 FS_STATE_OVLO3
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
FS_STATE_TRIM_CRC_SEC_FAULT FS_STATE_CFG_CRC_SEC_FAULT VCE_CLMP_HLD_TIME FS_STATE_CLK_MON_SEC_FAULT
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-16 CFG11 Register Field Descriptions
Bit Field Type Reset Description
15-14 FS_STATE_UVLO2 R/W 0x0

OUTH/OUTL state during an unmasked VCC2 UVLO fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
13-12 FS_STATE_OVLO2 R/W 0x0

OUTH/OUTL state during an unmasked VCC2 OVLO fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
11-10 FS_STATE_UVLO3 R/W 0x0

OUTH/OUTL state during an unmasked VEE2 UVLO fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
9-8 FS_STATE_OVLO3 R/W 0x0

OUTH/OUTL state during an unmasked VEE2 OVLO fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
7-6 FS_STATE_TRIM_CRC_SEC_FAULT R/W 0x0

OUTH/OUTL state during an unmasked TRIM CRC fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
5-4 FS_STATE_CFG_CRC_SEC_FAULT R/W 0x0

OUTH/OUTL state during an unmasked configuration register CRC fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action
3-2 VCE_CLMP_HLD_TIME R/W 0x0

Hold time for the VCE_CLMP function

0x0 = 100ns

0x1 = 200ns

0x2 = 300ns

0x3 = 400ns
1-0 FS_STATE_CLK_MON_SEC_FAULT R/W 0x0

OUTH/OUTL state during an unmasked clock monitor fault:

0x0 = Pulled Low

0x1 = Pulled High

0x2 = Reserved

0x3 = No action

7.6.1.12 ADCDATA1 Register

ADCDATA1 is shown in Figure 7-56 and described in Table 7-17. ADCDATA1 holds digital representation of AI1 input voltage.

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Figure 7-56 ADCDATA1 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-17 ADCDATA1 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI1 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI1. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI1 R 0x0

DATA_AI1 holds the data from the last AI1 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI1 = DATA_AI1(decimal) × 3.519mV

7.6.1.13 ADCDATA2 Register

ADCDATA2 is shown in Figure 7-57 and described in Table 7-18.DCDATA2 holds digital representation of AI3 input voltage.

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Figure 7-57 ADCDATA2 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-18 ADCDATA2 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI3 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI3. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI3 R 0x0

DATA_AI3 holds the data from the last AI3 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI3 = DATA_AI3(decimal) × 3.519mV

7.6.1.14 ADCDATA3 Register

ADCDATA3 is shown in Figure 7-58 and described in Table 7-19.DCDATA2 holds digital representation of AI5 input voltage.

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Figure 7-58 ADCDATA3 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-19 ADCDATA3 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI5 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI5. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI5 R 0x0

DATA_AI5 holds the data from the last AI5 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI5 = DATA_AI5(decimal) × 3.519mV

7.6.1.15 ADCDATA4 Register

ADCDATA4 is shown in Figure 7-59 and described in Table 7-20.DCDATA2 holds digital representation of AI2 input voltage.

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Figure 7-59 ADCDATA4 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-20 ADCDATA4 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI2 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI2. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI2 R 0x0

DATA_AI2 holds the data from the last AI2 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI2 = DATA_AI2(decimal) × 3.519mV

7.6.1.16 ADCDATA5 Register

ADCDATA5 is shown in Figure 7-60 and described in Table 7-21.Data field of AI4 ADC conversion result

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Figure 7-60 ADCDATA5 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-21 ADCDATA5 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI4 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI4. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI4 R 0x0

DATA_AI4 holds the data from the last AI4 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI4 = DATA_AI4(decimal) × 3.519mV

7.6.1.17 ADCDATA6 Register

ADCDATA6 is shown in Figure 7-61 and described in Table 7-22.Data field of AI6 ADC conversion result

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Figure 7-61 ADCDATA6 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-22 ADCDATA6 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_AI6 ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on AI6. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_AI6 R 0x0

DATA_AI6 holds the data from the last AI6 ADC measurement. Convert the measurement to a voltage using the following equation:

VAI6 = DATA_AI6(decimal) × 3.519mV

7.6.1.18 ADCDATA7 Register

ADCDATA7 is shown in Figure 7-62 and described in Table 7-23.Data field of internal die temperature ADC conversion result

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Figure 7-62 ADCDATA7 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-23 ADCDATA7 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_DTEMP ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on internal die temperature. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_DTEMP R 0x0

DATA_DTEMP holds the data from the last secondary side junction temperature ADC measurement. Convert the measurement to a temperature using the following equation:

TJ = DATA_DTEMP(decimal) × 0.7015°C - 198.36°C

Updated equation for PG2.1

7.6.1.19 ADCDATA8 Register

ADCDATA8 is shown in Figure 7-63 and described in Table 7-24.Data field of divided OUTH ADC conversion result

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Figure 7-63 ADCDATA8 Register
15 14 13 12 11 10 9 8
TIME_STAMP DATA
R-0x0 R-0x0
7 6 5 4 3 2 1 0
DATA
R-0x0
Table 7-24 ADCDATA8 Register Field Descriptions
Bit Field Type Reset Description
15-10 TIME_STAMP R 0x0

TIME_STAMP holds the time stamp for the DATA_OUTH ADC measurement. The time stamp counter is incremented with every transition on INP, but the TIME_STAMP bits are only updated with a valid ADC conversion on VGTH. Once the counter reaches 63, it rolls over to 0 on the next edge.
9-0 DATA_OUTH R 0x0

DATA_OUTH holds the data from the last power transistor gate threshold ADC measurement. Convert the measurement to a voltage using the following equation:

VGTH = DATA_OUTH(decimal) × 3.519mV

7.6.1.20 CRCDATA Register

CRCDATA is shown in Figure 7-64 and described in Table 7-25.

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Figure 7-64 CRCDATA Register
15 14 13 12 11 10 9 8
CRC_TX
R/W-0xFF
7 6 5 4 3 2 1 0
CRC_RX
R-0xFF
Table 7-25 CRCDATA Register Field Descriptions
Bit Field Type Reset Description
15-8 CRC_TX R/W 0xFF

CRC_TX holds the CRC for the received SPI data. The CRC is continuously updated as SPI messages are received. CRC_TX is reset when the bits are written, triggering a comparison. If the comparison fails, the STATUS2[SPI_FAULT] is set.
7-0 CRC_RX R 0xFF

CRC_RX holds the CRC for the sent SPI data. The CRC is continuously updated as the SPI messages are sent from SDO. CRC_RX is reset when CONTROL1[CLR_SPI_CRC] is written to '1'.

7.6.1.21 SPITEST

SPITEST is shown in Figure 7-65 and described in Table 7-26.

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Figure 7-65 SPITEST Register
15 14 13 12 11 10 9 8
SPI_TEST
R/W-0x0
7 6 5 4 3 2 1 0
SPI_TEST SPI_TEST
R/W-0x0 R/W-0x0
Table 7-26 SPITEST Register Field Descriptions
Bit Field Type Reset Description
15-0 SPI_TEST R/W 0x0

Writing non-zero value to SPI_TEST triggers the STATUS2[CFG_CRC_PRI_FAULT].

7.6.1.22 GDADDRESS Register

GDADDRESS is shown in Figure 7-66 and described in Table 7-27.

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Figure 7-66 GDADDRESS Register
15 14 13 12 11 10 9 8
RESERVED
R-0x0
7 6 5 4 3 2 1 0
RESERVED GD_ADDR
R-0x0 R-0x0
Table 7-27 GDADDRESS Register Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED R 0x0

This bit field is reserved.
3-0 GD_ADDR R 0x0

GD_ADDR stores the chip address. This field is updated during Configuration 1 when using the SPI Addressing mode. See the Section 8.1.2 section for more details.

7.6.1.23 STATUS1 Register

STATUS1 is shown in Figure 7-67 and described in Table 7-28.

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Figure 7-67 STATUS1 Register
15 14 13 12 11 10 9 8
INP_STATE INN_STATE RESERVED EN_STATE RESERVED OPM
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x1
7 6 5 4 3 2 1 0
OPM PWM_COMP_CHK_FAULT RESERVED GD_TWN_PRI_FAULT RESERVED
R-0x1 R-0x0 R-0x0 R-0x0 R-0x0
Table 7-28 STATUS1 Register Field Descriptions
Bit Field Type Reset Description
15 INP_STATE R 0x0

Indicates the input signal logic level at IN+:

0x0 = LOW

0x1 = HIGH
14 INN_STATE R 0x0

Indicates the input signal logic level at IN-:

0x0 = LOW

0x1 = HIGH
13-12 RESERVED R 0x0

This bit field is reserved.
11 ASC_EN_STATE R 0x0

Indicates the input signal logic level at pin ASC_EN:

0x0 = LOW

0x1 = HIGH
10-9 RESERVED R 0x0

This bit field is reserved.
8-6 OPM R 0x1

Indicates the current operational state of the device:

0x0 = Error

0x1 = Configuration 1

0x2 = Configuration 2

0x3 = Active

0x4 = Error

0x5 = Error

0x6 = Error

0x7 = Error
5 PWM_COMP_CHK_FAULT R 0x0

PWM comparison function check triggers a fault when the input to the secondary side is not the same as the IN+ input:

0x0 = No fault

0x1 = Fault
4-2 RESERVED R 0x0

This bit field is reserved.
1 GD_TWN_PRI_FAULT R 0x0

Gate driver over temperature warning triggers a fault when the temperature of the primary (VCC1)side is greater than the TWN_SET threshold. This bit is cleared when the temperature drops below the threshold, followed by a read of the STATUS1 register:

0x0 = No fault

0x1 = Fault
0 RESERVED R 0x0

This bit field is reserved.

7.6.1.24 STATUS2 Register

STATUS2 is shown in Figure 7-68 and described in Table 7-29.

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Figure 7-68 STATUS2 Register
15 14 13 12 11 10 9 8
RESERVED PRI_RDY UVLO1_FAULT OVLO1_FAULT STP_FAULT VREG1_ILIM_FAULT SPI_FAULT INT_REG_PRI_FAULT
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
INT_COMM_PRI_FAULT BIST_PRI_FAULT CLK_MON_PRI_FAULT CFG_CRC_PRI_FAULT TRIM_CRC_PRI_FAULT DRV_EN_RCVD OR_NFLT1_PRI OR_NFLT2_PRI
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
Table 7-29 STATUS2 Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0x0

This bit field is reserved.
14 PRI_RDY R 0x0

Primary side is ready for operations:

0x0 = Not ready

0x1 = Ready
13 UVLO1_FAULT R 0x0

A UVLO1_FAULT fault is triggered when VVCC1 < VUVLO1_LEVEL:

0x0 = No fault

0x1 = Fault
12 OVLO1_FAULT R 0x0

A OVLO1_FAULT fault is triggered when VVCC1 > VOVLO1_LEVEL:

0x0 = No fault

0x1 = Fault
11 STP_FAULT R 0x0

A Shoot-through protection fault is triggered when the IN- and IN+ logic levels are high at the same time:

0x0 = No fault

0x1 = Fault
10 VREG1_ILIMIT_FAULT R 0x0

A VREG1_ILIMIT_FAULT fault is triggered when the VREG1 current limit is active:

0x0 = No fault

0x1 = Fault
9 SPI_FAULT R 0x0

A SPI communication fault is triggered when nCS transitions low and high without receiving a proper amount of SCLK pulses (multiple of 16) or mismatch in the CRC_TX data written by the user. This bit is cleared when a valid SPI command is received, followed by a read of the STATUS2 register:

0x0 = No fault

0x1 = Fault
8 INT_REG_PRI_FAULT R 0x0

A primary side internal regulator fault is triggered when an internal rail on the primary side (including VREG1) experiences an OV or UV event:

0x0 = No fault

0x1 = Fault
7 INT_COMM_PRI_FAULT R 0x0

A primary side internal communication fault is triggered when the communication from the secondary to the primary side is disrupted:

0x0 = No fault

0x1 = Fault
6 BIST_PRI_FAULT R 0x0

A primary side BIST diagnosis fault is triggered when the latent check BIST fails during primary side power-up:

0x0 = No fault

0x1 = Fault
5 CLK_MON_PRI_FAULT R 0x0

A primary side Clock monitor fault is triggered when the received clock from the secondary side is mismatched from the primary clock:

0x0 = No fault

0x1 = Fault
4 CFG_CRC_PRI_FAULT R 0x0

A primary side configuration register CRC fault is triggered if a configuration bit for the primary side registers (CFG1, CFG2, CF3) changes while in ACTIVE mode. Additionally, CFG_CRC_PRI_FAULT is set if the SPITEST register or one of the RESERVED bits in the primary side registers is written while in the Configuration 2 state:

0x0 = No fault

0x1 = Fault
3 TRIM_CRC_PRI_FAULT R 0x0

A primary side internal data CRC fault is triggered if one of the internal bits held in memory changes. The trim register CRC is monitored in Configuration 2 and ACTIVE states:

0x0 = No fault

0x1 = Fault
2 DRV_EN_RCVD R 0x0

Indicates if a DRV_EN command has been received.

0x0=Driver not enabled

0x1=Driver is enabled
1 OR_NFLT1_PRI R 0x0

Indicates the logic OR of all primary side faults reporting to pin nFLT1.
0 OR_NFLT2_PRI R 0x0

Indicates the logic OR of all primary side faults reporting to pin nFLT2.

7.6.1.25 STATUS3 Register

STATUS3 is shown in Figure 7-69 and described in Table 7-30.

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Figure 7-69 STATUS3 Register
15 14 13 12 11 10 9 8
GM_STATE GM_FAULT INT_REG_SEC_FAULT INT_COMM_SEC_FAULT MCLP_STATE OVLO3_FAULT UVLO3_FAULT OVLO2_FAULT
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
UVLO2_FAULT VCEOV_FAULT PS_TSD_FAULT RESERVED VREG2_ILIMIT_FAULT SC_FAULT OC_FAULT DESAT_FAULT
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
Table 7-30 STATUS3 Register Field Descriptions
Bit Field Type Reset Description
15 GM_STATE R 0x0

Indicates the logic state of power transistor gate voltage. The gate is monitored using OUTH or OUTL depending on the expected output state of the driver (OUTL monitored when OUTH is pulled high and vice versa):

0x0 = LOW

0x1 = HIGH
14 GM_FAULT R 0x0

Gate voltage monitor fault is triggered when the GM_STATE does not match expected output:

0x0 = No fault

0x1 = Fault
13 INT_REG_SEC_FAULT R 0x0

Internal regulator fault:

0x0 = No fault

0x1 = Fault
12 INT_COMM_SEC_FAULT R 0x0

A secondary side internal regulator fault is triggered when an internal rail on the secondary side (including VREG2) experiences an OV or UV event:

0x0 = No fault

0x1 = Fault
11 MCLP_STATE R 0x0

Indicates the Active Miller clamp output state:

0x0 = Active Miller clamp is not active. VOUTH> VCLPTH

0x1 = Active Miller clamp is active. VOUTH< VCLPTH
10 OVLO3_FAULT R 0x0

A OVLO3_FAULT fault is triggered when VVEE2 < VOVLO3TH. CFG4[UVOV3_EN] must be '1' to enable VEE2 OV and UV faults:

0x0 = No fault

0x1 = Fault
9 UVLO3_FAULT R 0x0

A UVLO3_FAULT fault is triggered when VVEE2 > VUVLO3TH. CFG4[UVOV3_EN] must be '1' to enable VEE2 OV and UV faults:

0x0 = No fault

0x1 = Fault
8 OVLO2_FAULT R 0x0

A OVLO2_FAULT fault is triggered when VVCC2 > VOVLO2TH. CFG4[OV2_DIS] must be '0' to enable VCC2 OV faults:

0x0 = No fault

0x1 = Fault
7 UVLO2_FAULT R 0x0

A UVLO2_FAULT fault is triggered when VVCC2 < VUVLO2TH. CFG4[UV2_DIS] must be '0' to enable VCC2 UV faults:

0x0 = No fault

0x1 = Fault
6 VCEOV_FAULT R 0x0

Indicates that the active VCE clamp function triggered a soft-turn off event. CFG4[VCECLP_EN] must be '1' to enable VCEOV_FAULT:

0x0 = No fault

0x1 = Fault
5 PS_TSD_FAULT R 0x0

One of the enabled power switch temperature inputs (AI1, AI3, AI5) is above the PS_TSDTH threshold:

0x0 = No fault

0x1 = Fault
4 RESERVED R 0x0

This bit field is reserved.
3 VREG2_ILIMIT_FAULT R 0x0

A VREG2_ILIMIT_FAULT fault is triggered when the VREG2 current limit is active:

0x0 = No fault

0x1 = Fault
2 SC_FAULT R 0x0

One or more of the enabled power switch current inputs (AI2, AI4, AI6) is above the SCTH threshold indicating a short circuit fault:

0x0 = No fault

0x1 = Fault
1 OC_FAULT R 0x0

One or more of the enabled power switch current inputs (AI2, AI4, AI6) is above the OCTH threshold indicating a, over current fault:

0x0 = No fault

0x1 = Fault
0 DESAT_FAULT R 0x0

DESAT fault is triggered when VDESAT > VDESATTH indicating an over current fault:

0x0 = No fault

0x1 = Fault

7.6.1.26 STATUS4 Register

STATUS4 is shown in Figure 7-70 and described in Table 7-31.

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Figure 7-70 STATUS4 Register
15 14 13 12 11 10 9 8
RESERVED VCE_STATE GD_TWN_SEC_FAULT GD_TSD_SEC_FAULT RESERVED OR_NFLT1_SEC OR_NFLT2_SEC BIST_SEC_FAULT
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
CLK_MON_SEC_FAULT CFG_CRC_SEC_FAULT TRIM_CRC_SEC_FAULT RESERVED SEC_RDY
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
Table 7-31 STATUS4 Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0x0

This bit field is reserved.
14 VCE_STATE R 0x0

State of VCE voltage:

0x0 = Low

0x1 = High
13 GD_TWN_SEC_FAULT R 0x0

Gate driver over temperature warning triggers a fault when the temperature of the secondary (VCC2) side is greater than the TWN_SET threshold. This bit is cleared when the temperature drops below the threshold, followed by a read of the STATUS4 register:

0x0 = No fault

0x1 = Fault
12 GD_TSD_SEC_FAULT R 0x0

Gate driver thermal shutdown triggers a fault when the temperature of the secondary (VCC2) side is greater than the TSD_SET threshold:

0x0 = No fault

0x1 = Fault
11 RESERVED R 0x0

This bit field is reserved.
10 OR_NFLT1_SEC R 0x0

Indicates the logic OR of all secondary side faults reporting to pin nFLT1.
9 OR_NFLT2_SEC R 0x0

Indicates the logic OR of all secondary side faults reporting to pin nFLT2.
8 BIST_SEC_FAULT R 0x0

A secondary side BIST diagnosis fault is triggered when the latent check BIST fails during secondary side power-up:

0x0 = No fault

0x1 = Fault
7 CLK_MON_SEC_FAULT R 0x0

A secondary side clock monitor fault is triggered when the received clock from the primary side is mismatched from the secondary clock:

0x0 = No fault

0x1 = Fault
6 CFG_CRC_SEC_FAULT R 0x0

A secondary side configuration register CRC fault is triggered if a configuration bit for the secondary side registers (CFG4 - CF11) changes while in ACTIVE mode. Additionally, CFG_CRC_SEC_FAULT is set if the SPITEST register or one of the RESERVED bits in the secondary side registers is written while in the Configuration 2 state:

0x0 = No fault

0x1 = Fault
5 TRIM_CRC_SEC_FAULT R 0x0

A secondary side internal data CRC fault is triggered if one of the internal bits held in memory changes. The trim register CRC is monitored in Configuration 2 and ACTIVE states:

0x0 = No fault

0x1 = Fault
4-1 RESERVED R 0x0

This bit field is reserved
0 SEC_RDY R 0x0

Secondary side is ready for operations:

0x0 = Not ready

0x1 = Ready

7.6.1.27 STATUS5 Register

STATUS5 is shown in Figure 7-71 and described in Table 7-32.

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Figure 7-71 STATUS5 Register
15 14 13 12 11 10 9 8
ADC_FAULT Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESERVED
R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0 R-0x0
Table 7-32 STATUS5 Register Field Descriptions
Bit Field Type Reset Description
15 ADC_FAULT R 0x0

ADC_FAULT indicates that a fault has occurred in the VREF or during the ADC data transfer to the primary side. This fault only indicates faults when the ADC is enabled.

0x0 = No fault

0x1 = Fault condition. The VREF supply is out of range (OV, UV, or in current limit), or the IN+ signal is faster than guaranteed operation while ADC is enabled (30kHz).
14-0 RESERVED R 0x0

This bit field is reserved

7.6.1.28 CONTROL1 Register

CONTROL1 is shown in Figure 7-72 and described in Table 7-33. To write data in ACTIVE state, disable the configuration CRC check by setting CRC_DIS=1 before writing the data. The only exception to this is the CLR_SPI_CRC bit. This bit can be written in ACTIVE mode without disabling the CRC.

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Figure 7-72 CONTROL1 Register
15 14 13 12 11 10 9 8
CLR_SPI_CRC RESERVED CFG_CRC_CHK_PRI
R/W-0x0 R-0x0 R/W-0x0
7 6 5 4 3 2 1 0
PWM_COMP_CHK RESERVED STP_CHK RESERVED CLK_MON_CHK_PRI
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-33 CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
15 CLR_SPI_CRC R/W 0x0

Clear SPI CRC code:

0x0 = No

0x1 = Yes
14-9 RESERVED R 0x0

This bit field is reserved
8 CFG_CRC_CHK_PRI R/W 0x0

Run CRC check of configuration register bits of primary (VCC1) side:

0x0 = No

0x1 = Yes
7 PWM_COMP_CHK R/W 0x0

Run PWM signal comparison function check. PWM comparator generates PWM fault to set PWM_COMP_CHK_FAULT. This is only available in Configuration 2:

0x0 = No

0x1 = Yes
6 RESERVED R/W 0x0

This bit field is reserved
5 STP_CHK R/W 0x0

Run the check of STP function. shoot through protection generates STP fault to set STP_FAULT:

0x0 = No

0x1 = Yes
4-1 RESERVED R 0x0

This bit field is reserved
0 CLK_MON_CHK_PRI R/W 0x0

Run clock monitor check. Primary side clock monitor generates clock monitor fault to set CLK_MON_PRI_FAULT. SPI functions normally during this test:

0x0 = No

0x1 = Yes

7.6.1.29 CONTROL2 Register

CONTROL2 is shown in Figure 7-73 and described in Table 7-34. To write data in ACTIVE state, disable the configuration CRC check by setting CRC_DIS=1 before writing the data.

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Figure 7-73 CONTROL2 Register
15 14 13 12 11 10 9 8
CLR_STAT_REG RESERVED GATE_OFF_CHK GATE_ON_CHK VCECLP_CHK RESERVED DESAT_CHK SCP_CHK
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
OCP_CHK RESERVED VGTH_MEAS RESERVED CLK_MON_CHK_SEC CFG_CRC_CHK_SEC PS_TSD_CHK_SEC RESERVED
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 7-34 CONTROL2 Register Field Descriptions
Bit Field Type Reset Description
15 CLR_STAT_REG R/W 0x0

Clear status register. This bit is set back 0 once status register is cleared. Reading this bit always returns 0:

0x0 = No

0x1 = Yes
14 RESERVED R/W 0x0 This bit field is reserved.
13 GATE_OFF_CHK R/W 0x0

Check the continuity of gate turnoff path. The gate monitor comparator generates off-state fault to test the GM_FAULT while the gate is off. This function is used in ACTIVE mode with the CRC_DIS bit set. The MCU or the external controller controls IN+/IN- to turn off OUTH before sending this command. The gate driver output is pulled low and does not respond to IN+/IN- until GM_FAULT and this bit is cleared. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = OFF

0x1 = ON
12 GATE_ON_CHK R/W 0x0

Check the continuity of gate turnon path. The gate monitor comparator generates on-state fault to test the GM_FAULT while the gate is on. This function is used in ACTIVE mode with the CRC_DIS bit set. The gate driver output is pulled low. MCU or the external controller controls IN+/IN- to turn on OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = OFF

0x1 = ON
11 VCECLP_CHK R/W 0x0

Manual VCECLP BIST. The VCECLAMP comparator generates VCE over voltage fault to set VCEOV_FAULT. This function is used in ACTIVE mode with the CRC_DIS bit set. MCU or the external controller controls IN+/IN- to turn off OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = No

0x1 = Yes
10 RESERVED R/W 0x0

Reserved
9 DESAT_CHK R/W 0x0 Manual DESAT BIST. The DESAT comparator generates DESAT fault to set DESAT_FAULT. This function is used in ACTIVE mode with the CRC_DIS bit set. MCU or the external controller controls IN+/IN- to turn on OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = No

0x1 = Yes
8 SCP_CHK R/W 0x0

Manual SCP BIST. The SCP comparator generates short circuit fault to set SC_FAULT. This function is used in ACTIVE mode with the CRC_DIS bit set. MCU or the external controller controls IN+/IN- to turn on OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = No

0x1 = Yes
7 OCP_CHK R/W 0x0 Manual OCP BIST. The OCP comparator generates over current fault to set OC_FAULT. This function is used in ACTIVE mode with the CRC_DIS bit set. MCU or the external controller controls IN+/IN- to turn on OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = No

0x1 = Yes
6 RESERVED R/W 0x0

Reserved
5 VGTH_MEAS R/W 0x0

Run VGTH measurement function. Refer to the Section 7.3.5.14 section. This is only available in Configuration 2:

0x0 = No

0x1 = Yes
4 RESERVED R/W 0x0

Reserved
3 CLK_MON_CHK_SEC R/W 0x0

Manual clock monitor BIST. Secondary side clock monitor generates clock monitor fault to set CLK_MON_SEC_FAULT. SPI function normally during this test:

0x0 = No

0x1 = Yes
2 CFG_CRC_CHK_SEC R/W 0x0

Run CRC check of configuration bits of VCC2 side, Secondary side configuration CRC generates CRC fault to set CFG_CRC_SEC_FAULT:

0x0 = No

0x1 = Yes
1 PS_TSD_CHK_SEC R/W 0x0

Check power switch TSD protection function. The Power Switch over temperature protection generates over temperature fault to set PS_TSD_FAULT. This function is used in ACTIVE mode with the CRC_DIS bit set. MCU or the external controller controls IN+/IN- to turn on OUTH before sending this command. Ensure that the CRC_DIS bit is cleared after performing the necessary latent function checks to enable the CRC function:

0x0 = No

0x1 = Yes
0 RESERVED R/W 0x0 This bit field is reserved.

7.6.1.30 ADCCFG Register

ADCCFG is shown in Figure 7-74 and described in Table 7-35.

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Figure 7-74 ADCCFG Register
15 14 13 12 11 10 9 8
RESERVED ADC_ON_CH_SEL_7 ADC_ON_CH_SEL_6 ADC_ON_CH_SEL_5 ADC_ON_CH_SEL_4 ADC_ON_CH_SEL_3 ADC_ON_CH_SEL_2 ADC_ON_CH_SEL_1
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RESERVED ADC_OFF_CH_SEL_7 ADC_OFF_CH_SEL_6 ADC_OFF_CH_SEL_5 ADC_OFF_CH_SEL_4 ADC_OFF_CH_SEL_3 ADC_OFF_CH_SEL_2 ADC_OFF_CH_SEL_1
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R-0x0
Table 7-35 ADCCFG Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R/W 0x0 Reserved
14 ADC_ON_CH_SEL_7 R/W 0x0

The die temperature is enabled for sampling during the PWM ON ADC round robin. Die temperature data is returned to ADCDATA7. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
13 ADC_ON_CH_SEL_6 R/W 0x0

The AI6 channel is enabled for sampling during the PWM ON ADC round robin. AI6 data is returned to ADCDATA6. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
12 ADC_ON_CH_SEL_5 R/W 0x0

The AI4 channel is enabled for sampling during the PWM ON ADC round robin. AI4 data is returned to ADCDATA5. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
11 ADC_ON_CH_SEL_4 R/W 0x0

The AI2 channel is enabled for sampling during the PWM ON ADC round robin. AI2 data is returned to ADCDATA4. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
10 ADC_ON_CH_SEL_3 R/W 0x0

The AI5 channel is enabled for sampling during the PWM ON ADC round robin. AI5 data is returned to ADCDATA3. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
9 ADC_ON_CH_SEL_2 R/W 0x0

The AI3 channel is enabled for sampling during the PWM ON ADC round robin. AI3 data is returned to ADCDATA2. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
8 ADC_ON_CH_SEL_1 R/W 0x0

The AI1 channel is enabled for sampling during the PWM ON ADC round robin. AI1 data is returned to ADCDATA1. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
7 Reserved R/W 0x0 Reserved
6 ADC_OFF_CH_SEL7 R/W 0x0

The die temperature is enabled for sampling during the PWM OFF ADC round robin. Die temperature data is returned to ADCDATA7. The round robin sampling order is: AI1, AI3, AI5,AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
5 ADC_OFF_CH_SEL6 R/W 0x0

The AI6 channel is enabled for sampling during the PWM OFF ADC round robin. AI6 data is returned to ADCDATA6. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
4 ADC_OFF_CH_SEL5 R/W 0x0

The AI4 channel is enabled for sampling during the PWM OFF ADC round robin. AI4 data is returned to ADCDATA5. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
3 ADC_OFF_CH_SEL4 R/W 0x0

The AI2 channel is enabled for sampling during the PWM OFF ADC round robin. AI2 data is returned to ADCDATA4. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
2 ADC_OFF_CH_SEL3 R/W 0x0

The AI5 channel is enabled for sampling during the PWM OFF ADC round robin. AI5 data is returned to ADCDATA3. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
1 ADC_OFF_CH_SEL2 R/W 0x0

The AI3 channel is enabled for sampling during the PWM OFF ADC round robin. AI3 data is returned to ADCDATA2. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes
0 ADC_OFF_CH_SEL1 R/W 0x0

The AI1 channel is enabled for sampling during the PWM OFF ADC round robin. AI1 data is returned to ADCDATA1. The round robin sampling order is: AI1, AI3, AI5, AI2, AI4, AI6, Die Temp:

0x0 = No

0x1 = Yes

7.6.1.31 DOUTCFG Register

DOUTCFG is shown in Figure 7-75 and described in Table 7-36.

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Figure 7-75 DOUTCFG Register
15 14 13 12 11 10 9 8
AI1OT_EN AI3OT_EN AI5OT_EN AI2OCSC_EN AI4OCSC_EN AI6OCSC_EN FREQ_DOUT
RW-0x0 RW-0x0 RW-0x0 RW-0x1 RW-0x1 RW-0x0 R/W-0x0
7 6 5 4 3 2 1 0
RESERVED DOUT_TO_TJ DOUT_TO_AI6 DOUT_TO_AI4 DOUT_TO_AI2 DOUT_TO_AI5 DOUT_TO_AI3 DOUT_TO_AI1
R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R-0x0
Table 7-36 DOUTCFG Register Field Descriptions
Bit Field Type Reset Description
15 AI1OT_E R/W 0x0

AI1 Over Temperature protection for power FET:

0x0 = Disabled

0x1 = Enabled
14 AI3OT_EN R/W 0x0

AI3 Over Temperature protection for power FET:

0x0 = Disabled

0x1 = Enabled
13 AI5OT_EN R/W 0x0

AI5 Over Temperature protection for power FET:

0x0 = Disabled

0x1 = Enabled
12 AI2OCSC_EN R/W 0x1

AI2 Over Current / Short circuit protection for power FET:

0x0 = Disabled

0x1 = Enabled
11 AI4OCSC_EN R/W 0x1

AI4 Over Current / Short circuit protection for power FET:

0x0 = Disabled

0x1 = Enabled
10 AI6OCSC_EN R/W 0x0

AI6 Over Current / Short circuit protection for power FET:

0x0 = Disabled

0x1 = Enabled
9-8 FREQ_DOUT R/W 0x0

DOUT output frequency:

0x0 = 13.9kHz

0x1 = 27.8kHz

0x2 = 55.7kHz

0x3 = 111.4kHz
7 RESERVED R/W 0x0

Reserved
6 DOUT_TO_TJ R/W 0x0

Channel of die temp is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes
5 DOUT_TO_AI6 R/W 0x0

Channel AI6 is selected to output on DOUT. Only one channel can be selected at a time. :

0x0 = No

0x1 = Yes
4 DOUT_TO_AI4 R/W 0x0

Channel AI4 is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes
3 DOUT_TO_AI2 R/W 0x0

Channel AI2 is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes
2 DOUT_TO_AI5 R/W 0x0

Channel AI5 is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes
1 DOUT_TO_AI3 R/W 0x0

Channel AI3 is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes
0 DOUT_TO_AI1 R/W 0x0

Channel AI1 is selected to output on DOUT. Only one channel can be selected at a time.:

0x0 = No

0x1 = Yes