The primary communication between the IC and the external MCU is through an SPI bus that provides full-duplex communications in a controller-peripheral configuration. The external MCU is always a SPI controller that sends command requests on the SDI pin and receives device responses on the SDO pin. The device is always a SPI peripheral device that receives command requests and sends responses to the external MCU over the SDO line. The following lists the characteristics of the SPI:

• The SPI is a 4-pin interface.
• The frame size is 16 bits and is assigned as follows:
  Controller-to-peripheral (MCU to TUSS4440 over the SDI line)1 RW bit, 6 bits for the register address, 1 ODD parity bit for entire SPI frame, 8 bits for data

  Peripheral-to-controller (TUSS4440 to MCU over the SDO line)1 bit for Controller Parity error reporting during previous frame reception, 6 bits for the status, 1 bit for ODD parity for entire SPI frame, 8 bits for data
• SPI commands and data are shifted with the MSB first and the LSB last.
• The SDO line is sampled on the falling edge of the SCLK pin.
• The SDI line is shifted out on the rising edge of the SCLK pin.

The SPI communication begins with the NCS falling edge and ends with the NCS rising edge. The NCS high-level maintains the SPI peripheral-interface in the RESET state. The SDO output is in the tri-state condition.

The SPI does not support back-to-back SPI frame operation. After each SPI transfer the NCS pin must go from low to high before the next SPI transfer can begin.

Figure 7-8 shows an overview of a complete 16-bit SPI frame.

Figure 7-9 shows a SPI transfer sequence between the controller and the peripheral TUSS4440 device. When the controller is writing a SPI frame, the parity error bit indicates if there was a parity error for the previous frame. When the controller is transmitting the data for the SPI write, the peripheral echoes back register address that was sent just before in the command.

The status bits are defined in Table 7-4: