TUSS4440 has multiple modes to excite the transducer through OUTA and OUTB pins. For each of the modes, the desired frequency of burst is supplied through an external clock on the IOx pins. This enables the user to supply a highly precise clock calibrated to the center frequency of transducer to enable the highest sound pressure level generation. These modes can be selected by the IO_MODE bits in the DEV_CTRL_3 register.

The burst mode is enabled first, then the start of burst (OUTA/OUTB changing states) happens at the next falling edge of IO1 or IO2, depending on the mode selected. These modes are described below.

• IO_MODE = 0: In this mode, the external clock for the transducer is applied at the IO2 pin and the burst mode is enabled by setting the CMD_TRIGGER in the TOF_CONFIG register through SPI, as shown in Figure 7-1. The device then expects a clock at IO2 pin to generate pulses on the OUTA/OUTB pins. The start of burst happens from the first falling edge of IO2. The number of pulses are counted by counting falling edge to next falling edge transitions on IO2 once the start of burst is triggered. The end of burst sequence is signaled when the number of pulses defined in BURST_PULSE are sent, or when the CMD_TRIGGER = 0 is set through SPI, whichever occurs earlier. TI recommends that IO2 is held high before burst enable to count the number of pulses correctly. After the start of burst, the state of OUTA and OUTB pins are determined by IO1 and IO2 pins. A transition of CMD_TRIGGER from high to low to high again is required to initiate a new burst sequence.
  Figure 7-1 IO_MODE 0 Description
• IO_MODE = 1: In this mode, the external clock for the transducer is applied at the IO2 pin and the burst mode is enabled when IO1 pin transitions low (see Figure 7-2). The device then expects a clock at IO2 pin to generate pulses on the OUTA/OUTB pins. The start of burst happens from the first falling edge of IO2. The number of pulses are counted by counting falling edge to next falling edge transitions on IO2 once the start of burst is triggered. End of burst sequence is signaled when the number of pulses defined in BURST_PULSE are sent or IO1 transitions high, whichever occurs earlier. TI recommends that IO2 is held high before start of burst to count the number of pulse correctly. After the start of burst, the state of OUTA and OUTB pins are determined by IO1 and IO2 pins. A transition of IO1 from low to high to low again is required to initiate a new burst sequence.
  Figure 7-2 IO_MODE 1 Description
• IO_MODE = 2: In this mode both IO1 and IO2 are used to control OUTA and OUTB. The burst enable is triggered when either IO1 or IO2 transitions from high to low. Start of burst (OUTA and OUTB changing state) happens only at the next falling edge of IO1. Figure 7-3 shows the case where a high-to-low transition on IO2 is used to enable the burst. A burst is emulated when IO1 and IO2 are toggled in a non-overlapping sequence. After the start of burst, the state of OUTA and OUTB pins are determined by IO1 and IO2 pins. During a burst, if there is a condition where both IO1 and IO2 are high for more than half period of the internal clock f_{INT_CLK} (caused by differential delays due to PCB parasitics or MCU code), an end of burst and burst mode disable will be triggered. Any falling edge just after this condition will be ignored to toggle OUTA and OUTB as it would be considered as a new burst enable signal. A systematic condition of overlap can cause a continuous end of burst trigger such that OUTA and OUTB do not toggle even though IO1 and IO2 are toggling. TI recommends no overlap or minimum non-overlap between the IO1 and IO2 signals when measured at the pins. BURST_PULSE has no effect in this mode.
  Figure 7-3 IO_MODE 2 Description
• IO_MODE = 3: In this mode, burst enable and start of burst are both triggered by the falling edge of IO2. TI recommends that IO2 pin is kept pulled up to VDD for this mode. The device then expects a clock at IO2 pin to generate pulses on the OUTA/OUTB pins (see Figure 7-4). The number of pulses are counted by counting falling edge to next falling edge transitions on IO2 once the start of burst is triggered. End of burst sequence is signaled when the number of pulses defined in BURST_PULSE are sent. After end of burst, a blank-out timer interval defined by the DRV_PLS_FLT_DT register is started to prevent triggering of a new start of burst in the event if the IO2 pin is still toggling. After the start of burst, the state of OUTA and OUTB pins are determined by IO1 and IO2 pins.
  Figure 7-4 IO_MODE 3 Description