ZHCSKL1A December   2019  – May 2022 TUSS4440

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Transformer Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transformer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.7 Receiver Characteristics

over operating free-air temperature range, VVPWR, VVDRV and VVDD recommended voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
GLNALow-noise amplifier fixed gainLNA_GAIN = 0x00; fDRV_CLK = 58 KHz13.71516.8V/V
GLNALNA_GAIN = 0x01; fDRV_CLK = 58 KHz9.41012
GLNALNA_GAIN = 0x10; fDRV_CLK = 58 KHz17.62021.8
GLNALNA_GAIN = 0x11; fDRV_CLK = 58 KHz11.612.514.2
DRVIN_MINMinimum receive input(2)LOGAMP_DIS_FIRST=0x0;LOGAMP_DIS_LAST=0x0
LNA_GAIN=0x00; ERRLOG < ± 3dB; fDRV_CLK < 500KHz		2.4µVrms
DRVIN_MAXMaximum receive input(2)48mVrms
SLAFESlope of analog front end(4)VOUT_SCALE_SEL = 0x0; fDRV_CLK = 58 KHz2529.733mV/dB
VOUT_SCALE_SEL = 0x1; fDRV_CLK = 58 KHz3845.146
DRAFEReceiver path dynamic range (minimum to maximum input)(2)LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz		8292dB
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x1
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz		7486
LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1
ERRLOG < ± 3dB; fDRV_CLK < 500 KHz		5970
Receiver path dynamic Range (noise floor to maximum input)(3)LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0
ERRLOG < ± 3 dB; fDRV_CLK < 500 KHz		7484
BWLOGLogamp bandwidthInformation only401000KHz
INTLOGIntercept point in dBVLOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0;
fDRV_CLK = 40 KHz		-108-97dBV
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x1;
fDRV_CLK = 40 KHz		-94-86
LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1;
fDRV_CLK = 40 KHz		-80-70
ERRLOGLog conformance errorInformation only-33dB
fBPFConfigurable range of center frequency of BPFBPF_BYPASS = 0x0; BPF_FC_TRIM = 0x0;
set by different values of BPF_HPF_FREQ		40500KHz
QBPFQ of bandpass filterBPF_BYPASS = 0x0; BPF_Q_SEL = 0x0(1)345.2
RLPFInternal resistor on FLT pin to ground6.25KΩ
VO_PDSTLOutput pedestal level(2)VVDD = 3.3 V; fDRV_CLK = 40 KHz;  VOUT_SCALE_SEL = 0x0
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0		0.30.45V
VVDD = 5.0 V; fDRV_CLK = 40 KHz;  VOUT_SCALE_SEL = 0x1
LOGAMP_DIS_FIRST = 0x0;LOGAMP_DIS_LAST = 0x0		0.450.675
VN_pk_pkOutput peak-to-peak noiseVVDD=3.3 V; fDRV_CLK = 40 KHz; CFLT = 15 nF;  VOUT_SCALE_SEL = 0x0
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x0		50200mVpp
VVDD=5.0 V; fDRV_CLK = 40 KHz; CFLT = 15 nF;  VOUT_SCALE_SEL = 0x1
LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0		75300
(1) Other choices of Q possible.
(2) Measured with effectively very large CFLT. Actual minimum signal detectable will depend on VN_pk_pk.  Minimum and maximum input levels are defined by ERRLOG.
(3) Measured with different CFLT values according to Equation 3. Noise floor is set by VN_PK_PK in addition to VO_PDSTL.
(4) Slope measured with factory trim at fDRV_CLK = 58 KHz. Slope can be adjusted with LOGAMP_SLOPE_ADJ bits for different fDRV_CLK settings.