ZHCSKL1A December   2019  – May 2022 TUSS4440

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Transformer Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transformer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.1 Excitation Power Supply (VDRV)

The TUSS4440 device includes a current source which charges a capacitor connected to the VDRV pin. The VDRV pin serves as the power supply for the center tap of the transformer . The voltage on the VDRV pin (VVDRV) is controlled by an internal voltage monitor which can be configured by the VDRV_VOLTAGE_LEVEL bits. The current source is switched off after VDRV pin voltage crosses the configured VVDRV value. The charging current (IVDRV) can be configured using VDRV_CURRENT_LEVEL bits.

The use of VDRV pin has two advantages:

  • It allows device to be used in applications where VPWR values can violate absolute maximum parameter for the OUTA / OUTB pins.
  • In applications where VPWR can vary over a wide range, this allows the transducer drive voltage to be fixed for every burst for a deterministic sound pressure level created by the transducer. This is possible only when the minimum supply voltage on the VPWR pin is greater than the configured value of VVDRV

The VDRV regulation is disabled at device power up indicated by VDRV_HI_Z bit being set. To enable VDRV this bit must be cleared. This feature enables applications where the center tap of transformer is connected to a separate power supply source.

Note:
  • When VDRV pin is supplied from an external power supply, it must be ensured that all times including during power up, VVPWR > VVDRV + 0.3 V to prevent any reverse current from VDRV pin to VPWR pin. Alternatively a reverse current prevention diode can be used on VPWR pin as shown in Figure 8-1 (D1).
  • Very fast ramp-up rate on VPWR pin should be avoided to prevent damage to the device. If fast ramp rates are possible, a series resistor between power supply and VPWR pin as shown in Figure 8-1 (RPWR) is recommended.

After a burst is completed and during the long receive time (listen mode), the capacitor on VDRV pin will discharge causing the charging current to turn on intermittently. This can inject switching noise which can be picked by the analog front end as a spurious echo. To eliminate this noise, the DIS_VDRV_REG_LSTN bit can be set. This disables charging of VDRV automatically after the burst is done. The VDRV charging current can be turned on again by setting the VDRV_TRIGGER bit. Setting this bit may create a spurious echo which can be ignored by the echo processing in the MCU. The VDRV_READY bit in DEV_STAT register can be monitored to know when the required voltage level has been reached and the device is ready to generate a new burst. The VDRV_TRIGGER bit must be un-set through SPI just before the start of burst and will have to be set again for next charging cycle. If the VDRV_TRIGGER bit is not un-set before next burst cycle, the VDRV charging current will not be automatically disabled after the burst even when DIS_VDRV_REG_LSTN is set. This functionality is ignored when the VDRV_HI_Z bit is set.