ZHCSQM0 December   2022 TPSM82816

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 Output Discharge
      3. 8.3.3 COMP/FSET
      4. 8.3.4 MODE/SYNC
      5. 8.3.5 Spread Spectrum Clocking (SSC)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Power-Good Output (PG)
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PSM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short-Circuit Protection
      5. 8.4.5 Soft Start / Tracking (SS/TR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting the Output Voltage
        2. 9.2.2.2 Feedforward Capacitor
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Voltage Tracking
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Consideration
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.7 Power-Good Output (PG)

The device has a power-good output with window comparator. The PG pin goes high impedance after the FB pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls below 90% or rises higher than 110% of the nominal voltage (typical). Table 8-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.

Table 8-2 Power-Good Pin Logic
DEVICE STATEPG LOGIC STATUS
HIGH IMPEDANCELOW
Enabled (EN = High)0.95 × VFB_NOM ≤ VFB ≤ 1.07 × VFB_NOM

√

VFB < 0.9 × VFB_NOM or VFB > 1.1 × VFB_NOM√
Shutdown (EN = Low)√
UVLO

2 V ≤ VIN < VUVLO

√
Thermal Shutdown

TJ > TJSD

√
Power Supply Removal

VIN < 2 V

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The PG pin has a 40-μs deglitch time on the falling edge. See Figure 8-1.

Figure 8-1 Power-Good Transient and Delay Behavior