ZHCSTR3B December   2010  – November 2023 TPS53315

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP™ Integrated Circuit with Adaptive On-Time
      2. 6.3.2  Small Signal Model
      3. 6.3.3  Ramp Signal
      4. 6.3.4  Auto-Skip Eco-mode Light Load Operation
      5. 6.3.5  Adaptive Zero Crossing
      6. 6.3.6  Forced Continuous Conduction Mode
      7. 6.3.7  Power Good
      8. 6.3.8  Current Sense and Overcurrent Protection
      9. 6.3.9  Overvoltage and Undervoltage Protection
      10. 6.3.10 UVLO Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable and Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Circuit Diagram
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.1.2.2 Step 2: Select Switching Frequency
          3. 7.2.1.2.3 Step 3: Select the Inductance
          4. 7.2.1.2.4 Step 4: Select Output Capacitors
          5. 7.2.1.2.5 Step 5: Determine the Voltage-Divider Resistance (R1 and R2)
          6. 7.2.1.2.6 Step 6: Select the Overcurrent Resistance (RTRIP)
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit Diagram With Ceramic Output Capacitors
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.2.2.2 Step 2: Select Switching Frequency
          3. 7.2.2.2.3 Step 3: Select the Inductance
          4. 7.2.2.2.4 Step 4: Select Output Capacitance for Ceramic Capacitors
          5. 7.2.2.2.5 Step 5: Select the Overcurrent Setting Resistance (RTRIP)
        3. 7.2.2.3 External Component Selection When Using All Ceramic Output Capacitors
        4. 7.2.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.5 Electrical Characteristics

over recommended free-air temperature range, VDD = 12 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE AND SUPPLY CURRENT
VVINVIN pin power conversion input voltage315V
VDDSupply input voltage4.525V
IVIN(leak)VIN pin leakage currentVEN = 0 V1µA
IVDDVDD supply currentVDD current, TA = 25°C, No Load, VEN = 5 V,
VVFB = 0.630 V		420590µA
IVDDSDNVDD shutdown currentVDD current, TA = 25°C, No Load, VEN = 0 V10µA
INTERNAL REFERENCE VOLTAGE
VVFBVFB regulation voltageVFB voltage, CCM condition(1)0.6000V
TA = 25°C0.5970.6000.603V
TA = 0°C to 85°C0.59520.6000.6048
TA = –40°C to 85°C0.5940.6000.606
IVFBVFB input currentVVFB = 0.630 V, TA = 25°C0.0020.2µA
LDO OUTPUT
VVREGLDO output voltage0 mA ≤ IVREG ≤ 30 mA4.775.05.35V
IVREGLDO output current(1)Maximum current allowed from LDO30mA
VDOLDO drop out voltageVDD = 4.5 V, IVREG = 30 mA295mV
BOOT STRAP SWITCH
VFBSTForward voltageVVREG-VBST, IF = 10 mA, TA = 25°C0.10.2V
IVBSTLKVBST leakage currentVVBST = 23 V, VLL = 17 V, TA = 25°C0.011.5µA
DUTY AND FREQUENCY CONTROL
tOFF(min)Minimum off timeTA = 25°C150260400ns
tON(min)Minimum on timeVVIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to
VREG, TA = 25°C(1)		35
SOFTSTART
tSSInternal SS time from VOUT = 0 to
VOUT = 95%		RMODE = 39 kΩ0.7ms
RMODE = 100 kΩ1.4
RMODE = 200 kΩ2.8
RMODE = 470 kΩ5.6
POWERGOOD
VTHPGPG thresholdPG in from lower92.5%96%98.5%
PG in from higher107.5%110%112.5%
PG hysteresis2.5%5%7.8%
RPGPG transistor on-resistance153055Ω
tPGDELPG Delay after soft-start0.811.2ms
LOGIC THRESHOLD AND SETTING CONDITIONS
VENEN voltage thresholdEnable1.8V
Disable0.6
IENEN input currentVEN = 5 V1µA
fSWSwitching frequencyRRF = 0 Ω to GND, TA = 25°C(2)200250300kHz
RRF = 187 kΩ to GND, TA = 25°C(2)250300350
RRF = 619 kΩ to GND, TA = 25°C(2)350400450
RRF = Open, TA = 25°C(2)450500550
RRF = 866 kΩ to VREG, TA = 25°C(2)580650720
RRF = 309 kΩ to VREG, TA = 25°C(2)670750820
RRF = 124 kΩ to VREG, TA = 25°C(2)770850930
RRF = 0 Ω to VREG, TA = 25°C(2)8809701070
PROTECTION: CURRENT SENSE
ITRIPTRIP source currentVTRIP = 1 V, TA = 25°C9.410.010.6µA
TCITRIPTRIP current temperature coefficentOn the basis of 25°C(3)4700ppm/°C
VTRIPCurrent limit threshold setting rangeVTRIP-GND voltage0.21.2V
VOCLCurrent limit thresholdVTRIP = 1.2 V140150160mV
VTRIP = 0.2192633
VOCLNNegative current limit thresholdVTRIP = 1.2 V–160–150–140
VTRIP = 0.2 V–33–26–19
VAZCADJAuto zero cross adjustable rangePositive315mV
Negative–15–3
PROTECTION: UVP and OVP
VOVPOVP trip thresholdOVP detect115%120%125%
tOVPDELOVP propagation delay timeVFB delay with 50-mV overdrive1µs
VUVPOutput UVP trip threshold timeUVP detect65%70%75%
tUVPDELOutput UVP propagation delay time0.811.2ms
tUVPENOutput UVP enable delay timefrom EN to UVP workable, RMODE = 39 kΩ2.02.63.2ms
UVLO
VUVVREGVREG UVLO thresholdWake up4.004.204.32V
Hysteresis0.25
THERMAL SHUTDOWN
TSDNThermal shutdown thresholdShutdown temperature(3)145°C
Hysteresis(3)10
(1) Specified by design. Not production tested.
(2) Not production tested. Test condition is VIN = 12 V, VOUT= 1.1 V, IOUT= 5 A using application circuit shown in Figure 7-1.
(3) Specified by design. Not production tested.