10.1 Layout Guidelines
Considerations these design guidelines before beginning the application layout process.
- Design an input switching current loop as small as possible.
- Place the input capacitor close to the top switching FET.
- Design the output switching current loop as small as possible.
- The SW node must be physically small and as short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions.
- Bring Kelvin connections from the output to the feedback pin (VFB) of the device.
- Place analog and non-switching components far away from switching components.
- Make a single point connection from the signal ground to power ground.
- Do not allow switching current to flow under the device.