ZHCSMA7C january   2022  – december 2022 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 9.3.2  Capacitive Load Driving
        1. 9.3.2.1 FET Gate Slew Rate Control
        2. 9.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 9.3.3  Overcurrent and Short-Circuit Protection
        1. 9.3.3.1 Overcurrent Protection With Auto-Retry
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
      4. 9.3.4  Short-Circuit Protection
      5. 9.3.5  Analog Current Monitor Output (IMON)
      6. 9.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 9.3.7  Device Functional Mode (Shutdown Mode)
      8. 9.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 9.3.9  Output Reverse Polarity Protection
      10. 9.3.10 TPS4811x-Q1 as a Simple Gate Driver
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 10.3.1 Design Requirements
      2. 10.3.2 External Component Selection
      3. 10.3.3 Application Curves
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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10.4 Power Supply Recommendations

When the external MOSFETs turn OFF during the conditions such as INP control, overvoltage cutoff, overcurrent protection causing an interruption of the current flow, the input parasitic line inductance generates a positive voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include:

  • Use of a TVS diode and input capacitor filter combination across input to and GND to absorb the energy and dampen the positive transients.
  • Use of a diode or a TVS diode across the output and GND to absorb negative spikes.

The TPS4811-Q1 gets powered from the VS pin. Voltage at this pin must be maintained above V(VS_PORR) level to ensure proper operation. If the input power supply source is noisy with transients, then TI recommends to place a RVS - CVS filter between the input supply line and VS pin to filter out the supply noise. TI recommends RVS value around 100 Ω.

In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between ISCP and CS- pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI recommends to add filter capacitor of 1 nF (CSCP) across ISCP and CS- pins close to the device. Because nuisance trips are dependent on the system and layout parasitics, TI recommends to test the design in a real system and tweaked as necessary.

The following figure shows the circuit implementation with optional protection components.

GUID-20221206-SS0I-RWXG-N1NS-HMFXXKLTMSND-low.svgFigure 10-18 Circuit Implementation With Optional Protection Components for TPS4811-Q1