ZHCSMA7C january   2022  – december 2022 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 9.3.2  Capacitive Load Driving
        1. 9.3.2.1 FET Gate Slew Rate Control
        2. 9.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 9.3.3  Overcurrent and Short-Circuit Protection
        1. 9.3.3.1 Overcurrent Protection With Auto-Retry
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
      4. 9.3.4  Short-Circuit Protection
      5. 9.3.5  Analog Current Monitor Output (IMON)
      6. 9.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 9.3.7  Device Functional Mode (Shutdown Mode)
      8. 9.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 9.3.9  Output Reverse Polarity Protection
      10. 9.3.10 TPS4811x-Q1 as a Simple Gate Driver
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 10.3.1 Design Requirements
      2. 10.3.2 External Component Selection
      3. 10.3.3 Application Curves
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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9.3.3.2 Overcurrent Protection With Latch-Off

Connect an approximately 100-kΩ resistor across CTMR as shown in Figure 9-12. With this resistor, during the charging cycle, the voltage across CTMR gets clamped to a level below V(TMR_OC) resulting in a latch-off behavior.

Use Equation 9 to calculate CTMR capacitor to be connected between TMR and GND for RTMR = 100-kΩ.

Equation 9. C T M R = t O C R T M R   ×   l n 1 1 - 1.2 R T M R   ×   I T M R

Where, ITMR is internal pull-up current of 82-µA, tOC is desired overcurrent response time.

Toggle INP or EN/UVLO (below V(ENF)) or power cycle VS below V(VS_PORF) to reset the latch. At low edge, the timer counter is reset and CTMR is discharged. PU pulls up to BST when INP is pulled high.

GUID-20221207-SS0I-FHN9-NZ6D-FGFS9HSPMSW8-low.svg Figure 9-11 Overcurrent Protection With Latch-Off