ZHCSMA7C january   2022  – december 2022 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 9.3.2  Capacitive Load Driving
        1. 9.3.2.1 FET Gate Slew Rate Control
        2. 9.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 9.3.3  Overcurrent and Short-Circuit Protection
        1. 9.3.3.1 Overcurrent Protection With Auto-Retry
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
      4. 9.3.4  Short-Circuit Protection
      5. 9.3.5  Analog Current Monitor Output (IMON)
      6. 9.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 9.3.7  Device Functional Mode (Shutdown Mode)
      8. 9.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 9.3.9  Output Reverse Polarity Protection
      10. 9.3.10 TPS4811x-Q1 as a Simple Gate Driver
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 10.3.1 Design Requirements
      2. 10.3.2 External Component Selection
      3. 10.3.3 Application Curves
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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9.3.3.1 Overcurrent Protection With Auto-Retry

The CTMR programs the over current protection delay (tOC) and auto-retry time (tRETRY). Once the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 82-µA pull-up current. After the CTMR charges up to V(TMR_FLT), FLT_I asserts low providing warning on impending FET turn OFF. After CTMR charges to V(TMR_OC), PD pulls low to SRC turning OFF the FET. Post this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V(TMR_LOW) level, the capacitor starts charging with 2.5-uA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT_I de-asserts after de-assertion delay of 260 µs.

Use Equation 7 to calculate the CTMR capacitor to be connected across TMR and GND.

Equation 7. C T M R = I T M R   ×   t O C 1.2

Where, ITMR is internal pull-up current of 82-µA, tOC is desired overcurrent response time.

Use Equation 8 to calculate the TFLT_I duration.

Equation 8. T F L T_I = 1.1   ×   C T M R 82   μ

Where, TFLT_I is the FLT_I assertion delay.

The auto-retry time can be computed as, tRETRY = 22.7 × 106 × CTMR

If the overcurrent pulse duration is below tOC then the FET remains ON and CTMR gets discharged using internal pull down switch.

GUID-20221207-SS0I-HCWL-QQ3P-ZHKJQZJPKNVF-low.svg Figure 9-10 Overcurrent Protection With Auto-Retry