ZHCS155C March   2011  – November 2023 TPS40170

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Equations for Programming the Input UVLO:
      3. 6.3.3  Oscillator and Voltage Feed-Forward
        1. 6.3.3.1 Calculating the Timing Resistance (RRT)
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Soft-Start and Fault-Logic
        1. 6.3.5.1 Soft Start During Overcurrent Fault
        2. 6.3.5.2 Equations for Soft Start and Restart Time
      6. 6.3.6  Overtemperature Fault
      7. 6.3.7  Tracking
      8. 6.3.8  Adaptive Drivers
      9. 6.3.9  Start-Up into Pre-Biased Output
      10. 6.3.10 Power Good (PGOOD)
      11. 6.3.11 PGND and AGND
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
      2. 6.4.2 Operation Near Minimum VIN (VVIN ≤ 4.5 V)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bootstrap Resistor
      2. 7.1.2 SW Node Snubber Capacitor
      3. 7.1.3 Input Resistor
      4. 7.1.4 LDRV Gate Capacitor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  List of Materials
        3. 7.2.2.3  Select a Switching Frequency
        4. 7.2.2.4  Inductor Selection (L1)
        5. 7.2.2.5  Output Capacitor Selection (C9)
        6. 7.2.2.6  Peak Current Rating of Inductor
        7. 7.2.2.7  Input Capacitor Selection (C1, C6)
        8. 7.2.2.8  MOSFET Switch Selection (Q1, Q2)
        9. 7.2.2.9  Timing Resistor (R7)
        10. 7.2.2.10 UVLO Programming Resistors (R2, R6)
        11. 7.2.2.11 Boot-Strap Capacitor (C7)
        12. 7.2.2.12 VIN Bypass Capacitor (C18)
        13. 7.2.2.13 VBP Bypass Capacitor (C19)
        14. 7.2.2.14 VDD Bypass Capacitor (C16)
        15. 7.2.2.15 SS Timing Capacitor (C15)
        16. 7.2.2.16 ILIM Resistor (R9, C17)
        17. 7.2.2.17 SCP Multiplier Selection (R5)
        18. 7.2.2.18 Feedback Divider (R10, R11)
        19. 7.2.2.19 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 第三方产品免责声明
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
      3. 8.1.3 Related Devices
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Pin Configuration and Functions

GUID-42977E9C-6AE7-478E-95EE-0D68C7EFC3B0-low.gif Figure 4-1 RGY PACKAGE, QFN-20 (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 9 — Analog signal ground. This pin must be electrically connected to power ground PGND externally.
BOOT 18 O Boot capacitor node for high-side FET gate driver. The boot capacitor is connected from this pin to SW.
COMP 8 O Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the FB pin.
ENABLE 1 I This pin must be high for the device to be enabled. If this pin is pulled low, the device is put in a low-power consumption shutdown mode.
FB 7 I Negative input to the error amplifier. The output voltage is fed back to this pin through a resistor divider network.
HDRV 17 O Gate driver output for the high-side FET.
ILIM 12 I A resistor from this pin to PGND sets the overcurrent limit. This pin provides source current used for overcurrent protection threshold setting.
LDRV 14 O Gate driver output for the low-side FET. Also, a resistor from this pin to PGND sets the multiplier factor to determine short-circuit current limit. If no resistor is present the multiplier defaults to 7 times the ILIM pin voltage.
M/S 3 I Primary or secondary mode selector pin for frequency synchronization. This pin must be tied to VIN for primary mode. In the secondary mode this pin must be tied to AGND or left floating. If the pin is tied to AGND, the device synchronizes with a 180° phase shift. If the pin is left floating, the device synchronizes with a 0° phase shift.
PGND 13 — Power ground. This pin must externally connect to the AGND at a single point.
PGOOD 11 O Power good indicator. This pin is an open-drain output pin and a 10 kΩ pull-up resistor is recommended to be connected between this pin and VDD.
RT 4 I A resistor from this pin to AGND sets the oscillator frequency. Even if operating in secondary mode, it is required to have a resistor at this pin to set the free running switching frequency.
SS 5 I Soft-start. A capacitor must be connected at this pin to AGND. The capacitor value sets the soft-start time.
SW 16 I This pin must connect to the switching node of the synchronous buck converter. The high-side and low-side FET current sensing are also done from this node.
SYNC 2 I/O Synchronization. This is a bi-directional pin used for frequency synchronization. In the primary mode, it is the SYNC output pin. In the secondary mode, it is a SYNC input pin. If unused, this pin can be left open.
TRK 6 I Tracking. External signal at this pin is used for output voltage tracking. This pin goes directly to the internal error amplifier as a positive reference. The lesser of the voltages between VTRK and the internal 600 mV reference sets the output voltage. If not used, this pin must be pulled up to VDD.
UVLO 20 I Undervoltage lockout. A resistor divider on this pin from VIN to AGND can be used to set the UVLO threshold.
VBP 15 O 8 V regulated output for gate driver. A ceramic capacitor with a value from 1 µF to 10 µF must be connected from this pin to PGND and placed close to this pin.
VDD 10 O 3.3 V regulated output. A ceramic by-pass capacitor with a value from 0.1 µF to 1 µF must be connected from this pin to AGND and placed close to this pin.
VIN 19 I Input voltage for the controller which is also the input voltage for the DC/DC converter. A ceramic by-pass capacitor with a value from 0.1 µF to 1 µF must be connected from this pin to PGND and placed close to this pin.
(1) I = input, O = output