ZHCSQB8B July   2021  – October 2022 TPS38700-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
      1.      Mechanical, Packaging, and Orderable Information

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I2C

Refer to Table 8-1 for the I2C register map overview. Note that "PSEQ" refers to TPS38700-Q1 and is used enhance table readability.

Table 8-1 I2C Register Categories and Associated Details
TYPE BITS DESCRIPTION RANGE / FUNCTION OR STATUS WHO TOGGLES THEM? WHO ELSE CAN WRITE TO THEM? WHAT GETS AFFECTED DUE TO THIS BIT?
OTP bits R VENDORID[7:0] TI defined TI defined OTP option None None
MODEL_REV[7:0] TI defined TI defined OTP option None None
TARGET_ID[7:0] TI defined TI defined OTP option None I2C
Interrupt info bits RW1C F_INTERR Internal fault No internal fault / Internal fault detected Interrupt Any of the interrupts generated; Can be cleared by writing 1 NIRQ
EM_PD (1) Emergency Power down No emergency PD / shutdown caused by emergency PD PSEQ PSEQ; SOC NRST; NIRQ
WDT Watchdog violation Did not occur / occurred Watchdog WD; SOC NIRQ; NRST (depends on if set in configuration register)
F_PEC Packet Error checking (PEC) PEC miscompare did not occur / occurred I2C I2C; SOC NIRQ
RTC RTC alarm has not triggered / triggered RTC RTC; SOC NIRQ
F_EN Enable output pin fault No faults detected / fault detected EN readback-PSEQ PSEQ; SOC NIRQ; NRST
F_OSC Crystal oscillator fault No faults detected / fault detected Frequency detector Frequency detector; SOC NIRQ
F_NRSTIRQ Reset or Interrupt pin fault No faults detected / fault detected Reset readback-PSEQ PSEQ; SOC NIRQ
F_BIST Built-In self test fault No faults detected / fault detected BIST BIST; SOC NIRQ; NRST
F_LDO LDO fault No faults detected / fault detected BIST BIST; SOC NIRQ; NRST
F_TSD Thermal shutdown fault No faults detected / fault detected TSD TSD; SOC NIRQ; NRST
F_RT_CRC Runtime CRC register fault No faults detected / fault detected CRC SOC NIRQ
F_ECC_DED ECC double error deduction on OTP load No ECC DED / ECC DED on OTP load NVM_ECC; REG_CRC NVM_ECC; REG_CRC; SOC NIRQ; NRST
F_PBSB (1) NPWR_BTN short press No short pulse / short pulse PSEQ PSEQ; SOC NRST; NIRQ
Status bits R ST_NIRQ Current state of NIRQ output NIRQ asserted / not asserted Interrupt None None
ST_NRST Current state of NRST output NRST asserted / not asserted Interrupt; NRSTstate change None None
ST_ACTSLP Current state of SLEEP input SLEEP pin driven Low or High PSEQ None None
ST_ACTSHDN Current state of ACT input ACT pin driven Low or High PSEQ None None
ST_PSEQ[1:0] Current state of PSEQ SHDNx, Power Up, Power Down, Sleep, Sleep entry, Sleep exit, invalid, Active PSEQ None None
STDR1 Current drive state of EN12 to EN9 Sequencer is driving EN Low or High PSEQ None None
STDR2 Current drive state of EN8 to EN1 Sequencer is driving EN Low or High PSEQ None None
OPEN Watchdog Open Window Watchdog update Window closed / open WD None None
WDUV Watchdog Update Violation No violation / WD updated too early WD None None
WDEXP Watchdog close timer expired WDT not expired / expired WD None None
BIST_C BIST state BIST not complete or executed / BIST complete BIST None None
ECC_SEC Status of ECC single error correction No error correction applied / SEC applied NVM_ECC None None
BIST_VM Status of volatile memory test output from BIST Volatile memory test pass / fail REG_CRC None None
BIST_NVM Status of non-volatile memory test output from BIST Non-Volatile memory test pass / fail OTP covered None None
BIST_L Status of Logic test ouput from BIST Logic test pass / fail BIST None NIRQ/ NRST
BIST_A Status of Analog test ouput from BIST Analog test pass / fail BIST None NIRQ/ NRST
OTP bits R EN_AF[12:9] Enable AF for EN12, EN11, EN10, EN9 Disabled/ Enabled OTP option None PSEQ
AFIO[12:9] Select AF for EN12, EN11, EN10, EN9 GPO or NPWR_BTN /NRST_IN/ NEM_PD OTP option None PSEQ
PP_EN[12:1] ENx pin driver configuration Open drain/ Push-Pull OTP option None IO
XTAL_LOAD Crystal oscillator load capacitance External/ Internal OTP option None XTAL
XTAL_EN Crystal oscillator Enable Crystal driver disabled/ enabled OTP option None XTAL
PP_CLK32K CLK32K pin driver configuration Open drain/ Push-Pull OTP option None XTAL
CONTROL R/W GPIO[12:9] General purpose input / outputs Open drain / Push-Pull SOC None PSEQ
Debounce[3:0] Debounce value for AF input pins 5 ms to 80 ms SOC None PSEQ
EN_DEB[12:9] Enable debounce for AF input pins Debouce disabled / enabled SOC None PSEQ
LP_TIME_TSHLD[7:0] NPWR_BTN long press time threshold 100 ms to 25.6 s SOC None PSEQ
RELOAD Reload OTP Reload or do not Reload when SEQ5 / 6 is complete SOC SOC OTP Register
FORCE_INT Force NIRQ low NIRQ contolled by faults / register SOC SOC NRST
FORCE_ACT Force PSEQ Active state SLEEP pin controls exit / entry or is ignored PSEQ SOC can clear it; but not set it PSEQ
FORCE_SHDN[1:0] Force PSEQ Shutdown state ACT pin control or Force SHDN and resume ACT pin control after delay SOC SOC; WDT PSEQ
RST_DLY[3:0] Reset Delay 0.1 ms to 128 ms SOC None PSEQ
RTC_WAKE Autonomous wake alarm enable Disabled / Enabled SOC None RTC
RTC_PU Autonomous RTC power up from SHDN2 to ACTIVE Disabled / Enabled SOC None RTC
REQ_PEC Require PEC byte (if EN_PEC = 1) Missing PEC is treated as good / bad SOC None I2C
EN_PEC Packet Error checking (PEC) PEC disabled / enabled SOC None I2C
AT_POR Run BIST at POR Skip / run BIST at POR SOC None BIST
AT_SHDN Run BIST when exiting SEQ5 / 6 Default to not run BIST SOC None BIST
PSEQ USLOT[3:0] Power Up / Sleep Exit time slots 125 μs / 2.5 s SOC None PSEQ
DSLOT[3:0] Power down / Sleep Entry time slots 125 μs / 2.5 s SOC None PSEQ
SSTEP Slot step multiplier 250 μs / 1000 μs SOC None PSEQ
PU[3:0][12:1] Power Up Sequence ENx not mapped / ENx mapped SOC None PSEQ
PD[3:0][12:1] Power Down Sequence ENx not mapped / ENx mapped SOC None PSEQ
SLP_EXT[3:0][12:1] Sleep Exit Sequence ENx not mapped / ENx mapped SOC None PSEQ
SLP_ENTRY[3:0][12:1] Sleep Entry Sequence ENx not mapped / ENx mapped SOC None PSEQ
RTC (2) RTC_T[31:0] RTC time setting 1 sec to 136 years XTAL; internal oscillator None RTC
RTC_A[31:0] RTC alarm setting 1 sec to 136 years SOC None RTC
WDT WDT_EN[1:0] Watchdog configuration Disabled / Enabled SOC None WDT
SLP_EN Automatic disable in Sleep mode Watchdog disabled / enabled in Sleep SOC None WDT
WDT_DLY[2:0] Delay in number of Watchdog periods 1 or 8 WDT period SOC None WDT
PDMD[1:0] Power down mode for WDT force power down Value written to CTL_1.FORCE_SHDN on WDT power down SOC None PSEQ
CLOSE[7:0] WDT close window configuration 1 ms to 864 ms SOC None WDT
OPEN[7:0] WDT open window configuration 1 ms to 864 ms SOC None WDT
KEY[7:0] WDT key to reset 0 / 1 SOC None WDT
PROT WRK Work set register lock 0 / 1 SOC only 1 None Write function to those register groups
SEQS SEQS set register lock 0 / 1 SOC only 1 None Write function to those register groups
SEQP SEQP set register lock 0 / 1 SOC only 1 None Write function to those register groups
SEQC SEQC set register lock 0 / 1 SOC only 1 None Write function to those register groups
WDT WDT set register lock 0 / 1 SOC only 1 None Write function to those reg groups
RTC RTC set register lock 0 / 1 SOC only 1 None Write function to those reg groups
CTL CTL set register lock 0 / 1 SOC only 1 None Write function to those reg groups
Presence of fault reporting functionality dependent on part configuration.
Register RTC_T must be written to before writing a value in register RTC_A.