ZHCSQB8C July   2021  – December 2022 TPS38700-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
      1.      Mechanical, Packaging, and Orderable Information

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8.4.1 Register Descriptions

Table 8-3 INT_SRC1

Address: 0x10

Description: Interrupt Source register. If F_INTERNAL, then INT_SRC2 register provides further information.

POR Value: 0x00

Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

F_INTERNAL

Internal Fault (ORed value of all bits in INT_SRC2): 0 = No internal fault detected

1 = Internal fault detected. Further detail flagged in INT_SRC2. This bit is cleared by clearing the bits in INT_SRC2.

6

EM_PD

Emergency Power Down:

0 = No emergency power-down event

1 = Shutdown caused by emergency power-down (Sequence 2).

Write-1-to-clear will clear the bit. The bit will be set again on next emergency power-down.

5

WDT

0 = WDT violation did not occur (or WDT_CFG.WDTEN[1:0] = 00b). 1 = WDT violation occurred.

This bit is valid only if WDT_CFG.WDTEN[1:0] is enabled.

Write-1-to-clear will clear the bit. The bit will be set again on next WDT violation.

4

PEC

Packet Error Checking:

0 = PEC miscompare has not occurred (or CTL_2.EN_PEC = 0). 1 = PEC miscompare has occurred.

This bit is valid only if CTL_2.EN_PEC is enabled.

Write-1-to-clear will clear the bit. The bit will be set again on next PEC miscompare.

3

RTC

0 = RTC alarm has not triggered (or alarm function is disabled). 1 = RTC alarm has triggered.

This bit is invalid if the alarm function is disabled (CTL_2.RTC_WAKE and CTL_2.RTC_PU are both clear, and RTC_A[31:0] is set to 0xFFFFFFFF.)

Write-1-to-clear will clear the bit. The bit will be set again on next RTC alarm.

2

F_EN

Enable Output Pin Fault:

0 = No short to supply or ground detected. 1 = Short to supply or ground detected.

Write-1-to-clear will clear the bit only if the fault condition is also removed.

1

F_OSC

Crystal Oscillator Fault:

0 = No fault detected on Crystal Oscillator (or CLK_CFG.XTAL_EN = 0, disabled). 1 = Fault detected on Crystal Oscillator.

Write-1-to-clear will clear the bit only if the fault condition is also removed.

0

F_NRSTIRQ

Reset or Interrupt Pin Fault:

0 = No fault detected on NRST or NIRQ.

1 = Low resistance path to supply detected on either NRST or NIRQ.

Write-1-to-clear will clear the bit only if the fault condition is also removed.

INT_SRC1 represents the reason that NIRQ was asserted. When the host processor receives NIRQ, it may read this register to quickly determine the source of the interrupt. If this register is clear, then TPS38700-Q1 did not assert NIRQ.

Table 8-4 INT_SRC2

Address: 0x11

Description: Interrupt Source register for internal errors.

POR Value: 0x00

Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

F_VENDOR

Vendor specific internal fault. Details reported in INT_VENDOR. This bit represents the ORed value of all bits in INT_VENDOR.

0 = No fault reported in INT_VENDOR 1 = Fault reported in INT_VENDOR

This bit is cleared by clearing the bits in INT_VENDOR.

6

RSVD

Reserved

5

F_RT_CRC

Runtime register CRC Fault:

0 = No fault detected.

1 = Register CRC fault detected.

Write-1-to-clear will clear the bit. The bit will be set again during next register CRC check if a fault is detected.

4

F_BIST

Built-In Self Test Fault:

0 = No fault detected.

1 = BIST fault detected.

Note that clearing this bit does not clear the results in TEST_STAT register.

Write-1-to-clear will clear the bit. The bit will be set again during next BIST execution if a fault is detected.

3

F_LDO

LDO Fault:

0 = No LDO fault detected. 1 = LDO fault detected.

If internal LDO is used, this flag is to indicate fault.

If internal LDO is not used, this flag must be reserved.

Write-1-to-clear will clear the bit only if the fault condition is also removed.

2

F_TSD

Thermal Shutdown:

0 = No thermal shutdown.

1 = Thermal shutdown occurred since last read.

Write-1-to-clear will clear the bit only if the fault condition is also removed.

1

F_ECC_DED

ECC Double-Error Detection on OTP configuration load:

0 = No ECC-DED on OTP load. 1 = ECC-DED on OTP load.

Write-1-to-clear will clear the bit. The bit will be set again during next OTP configuration load if a fault is detected.

0

F_PBSP

NPWR_BTN Short Pulse:

0 = No short pulse on NPWR_BTN (or NPWR_BTN is not enabled). 1 = Short pulse detected on NPWR_BTN.

This bit is valid only if NPWR_BTN is enabled through EN_AF12 and AFIO12 bits.

Write-1-to-clear will clear the bit. The bit will be set again during next short pulse detected on NPWR_BTN.

Table 8-5 INT_VENDOR

Address: 0x12

Description: Vendor Specific Internal Interrupt Status register.

POR Value: 0x00

Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

FAULTS[7:0]

Vendor specific internal faults flags.

Table 8-6 CTL_STAT

Address: 0x13

Description: TPS38700-Q1 Status register for control pins and internal state.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:6

RSVD

Reserved

5

ST_NIRQ

Current state of NIRQ Output:

0 = NIRQ pin asserted low by TPS38700-Q1.

1 = NIRQ pin not asserted low by TPS38700-Q1.

4

ST_NRST

Current state of NRST Output:

0 = NRST pin asserted low by TPS38700-Q1.

1 = NRST pin not asserted low by TPS38700-Q1.

3

ST_ACTSLP

Current state of SLEEP input:

0 = SLEEP pin driven low (Sleep) by system. 1 = SLEEP pin driven high (Active) by system.

2

ST_ACTSHDN

Current state of ACT input:

0 = ACT pin driven low (Shutdown) by system. 1 = ACT pin driven high (Active) by system.

1:0

ST_PSEQ[1:0]

00b: SHDNx, Power Up, Power Down

01b: SLEEP, Sleep Entry, Sleep Exit

10b: Invalid combination

11b: ACTIVE

Table 8-7 EN_STDR1

Address: 0x14

Description: Current drive status of Enable Pins.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3:0

STDR_EN[12:9]

Current drive state of EN[X]:

0 = TPS38700-Q1 is driving EN[X] Low.

1 = TPS38700-Q1 is driving or allowing to float EN[X] High
Table 8-8 EN_STDR2

Address: 0x15

Description: Current drive status of Enable Pins.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

STDR_EN[8:1]

Current drive state of EN[X]:

0 = TPS38700-Q1 is driving EN[X] Low.

1 = TPS38700-Q1 is driving or allowing to float EN[X] High

Table 8-9 EN_STRD1

Address: 0x16

Description: Current read status of Enable Pins.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3:0

STRD_EN[12:9]

Current read state of EN[X]:

0 = TPS38700-Q1 is reading EN[X] Low.

1 = TPS38700-Q1 is reading EN[X] High

Table 8-10 EN_STRD2

Address: 0x17

Description: Current read status of Enable Pins.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

STRD_EN[8:1]

Current read state of EN[X]:

0 = TPS38700-Q1 is reading EN[X] Low.

1 = TPS38700-Q1 is reading EN[X] High

Table 8-11 WDT_STAT

Address: 0x18

Description: WDT status register.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3

OPEN

Watchdog Open Window:

0 = Watchdog update window closed.

1 = Watchdog update window open.

2

RSVD

Reserved

1

WDUV

Watchdog Update Violation. Clear on read.

0 = No violation detected.

1 = Watchdog updated too early.

0

WDEXP

Watchdog close timer expired without update to WDKEY. Clear on read.

0 = WDT Not Expired.

1 = WDT Expired.

Table 8-12 TEST_STAT

Address: 0x19

Description: Internal Self-Test and ECC status register.

POR Value: 0x00

Access: Read only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

RSVD

Reserved

6

BIST_C

BIST state:

0 = BIST running or not executed since last POR. Check also TEST_CFG register.

1 = BIST complete.

5

ECC_SEC

Status of ECC Single-Error Correction on OTP configuration load.

0 = no error correction applied.

1 = Single-Error Correction applied.

4

RSVD

Reserved

3

BIST_VM

Status of Volatile Memory test output from BIST.

0 = Volatile Memory test pass.

1 = Volatile Memory test fail.

2

BIST_NVM

Status of Non-Volatile Memory test output from BIST.

0 = Non-Volatile Memory test pass.

1 = Non-Volatile Memory test fail.

1

BIST_L

Status of Logic test output from BIST.

0 = Logic test pass.

1 = Logic test fail.

0

BIST_A

Status of Analog test output from BIST.

0 = Analog test pass.

1 = Analog test fail.
Table 8-13 LAST_RST

Address: 0x1A

Description: Reason of last NRST assertion or shutdown. NRST assertion and shutdown occur in Sequence 2, Sequence 5, Sequence 6, Sequence 7, and Sequence 8.

The register is maintained as long as VDD and/or VBBAT is present. An emergency shutdown triggering Sequence 2 is already recorded in INT_SRC1.EM_PD register bit, so it does not need to be stored in this register. The host is expected to read this register as part of the first actions taken upon power ON.

The register is overwritten with new relevant data on next NRST assertion or shutdown.

POR Value: 0x00

Access: Read Only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

NRST_IN

NRST assertion due to NRST_IN (if enabled in EN_ALT_F and AF_IN_OUT registers).

0 = Last NRST assertion was not due to NRST_IN.

1 = Last NRST assertion was due to NRST_IN.

6

WDT_RST

NRST assertion due to WDT (see also Table 8-37).

0 = Last NSRT assertion was not due to WDT.

1 = Last NSRT assertion was due to WDT.

5

RSVD

Reserved

4

NEM_PD

NRST/Shutdown due to NEM_PD (if enabled in EN_ALT_F and AF_IN_OUT registers).

0 = Last NRST/Shutdown assertion was not due to NEM_PD.

1 = Last NRST/Shutdown assertion was due to NEM_PD.

3

ACTSHDN

NRST/Shutdown due to ACT asserted Low (shutdown).

0 = Last NRST/Shutdown assertion was not due to ACT Low.

1 = Last NRST/Shutdown assertion was due to ACT Low.

2

WDT_SHDN

NRST/Shutdown due to WDT (see also Table 8-37).

0 = Last NRST/Shutdown assertion was not due to ACT/ SHDN Low.

1 = Last NRST/Shutdown assertion was due to ACT/ SHDN Low.

If this bit is set, LAST_RST.FORCE_SHDN[1:0] contains WDT_CFG.PDMD[1:0] value.

1:0

FORCE_SHDN[1:0]

NRST/Shutdown due to CTL_1.FORCE_SHDN[1:0] ≠00b.

Value is the same as CTL_1.FORCE_SHDN[1:0] that initiated the last NRST/Shutdown. If WDT_SHDN bit is set, this bitfield contains WDT_CFG.PDMD[1:0] value.
Table 8-14 EN_ALT_F

Address: 0x20

Description: Enable Alternate Function for sequencing pins EN[12:9] (AF is selected in AF_IN_OUT register).

POR Value: Loaded from NVM

Access: Read only once loaded from NVM

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3

EN_AF12

Enable alternate function of EN[12]:

0 = Disabled.

1 = AF Enabled (GPO12 or NPWR_BTN).

2

EN_AF11

Enable alternate function of EN[11]:

0 = Disabled.

1 = AF Enabled (GPO11 or NRST_IN).

1

EN_AF10

Enable alternate function of EN[10]:

0 = Disabled.

1 = AF Enabled (GPO10 or NEM_PD).

0

EN_AF9

Enable alternate function of EN[9]:

0 = Disabled.

1 = AF Enabled (GPO9).

The alternate function can be enabled only if the corresponding PU/ PD/ SLP_EXIT/ SLP_ENTRY registers fields are all set to 0. If any of those bit fields are non-zero, the corresponding pin is locked to EN[X] sequencing function.

Table 8-15 AF_IN_OUT

Address: 0x21

Description: Select Alternate Function for sequencing pins EN[12:9] (AF is enabled in EN_ALT_F register).

POR Value: Loaded from NVM.

Access: Read only once loaded from NVM.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3

AFIO12

Select alternate function of EN12:

0 = General Purpose Output (GPO) - GPO12.

1 = AF NPWR_BTN (power button input).

2

AFIO11

Select alternate function of EN11:

0 = GPO11.

1 = AF NRST_IN (reset input).

1

AFIO10

Select alternate function of EN10:

0 = GPO10.

1 = AF NEM_PD (emergency power-down input).

0

AFIO9

Select alternate function of EN9:

0 = GPO9.

1 = Invalid.

EN9 can only be selected as GPO9 through EN_ALT_F.EN_AF9, and does not have an al- ternate function. Therefore, this bit is always read-only and should always read 0.
Table 8-16 EN_CFG1

Address: 0x22

Description: Drive mode configuration for EN[12:9]

POR Value: Loaded from NVM.

Access: Read only once loaded from NVM

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3:0

PP_EN[12:9]

ENx pin driver configuration:

0 = Open drain.

1 = Push pull.

Table 8-17 EN_CFG2

Address: 0x23

Description: Drive mode configuration for EN[8:1].

POR Value: Loaded from NVM.

Access: Read only once loaded from NVM.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

PP_EN[8:1]

ENx pin driver configuration:

0 = Open drain.

1 = Push pull.

Table 8-18 CLK_CFG

Address: 0x24

Description: Oscillator configuration.

POR Value: Loaded from NVM.

Access: Read only once loaded from NVM.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

XTAL_LOAD

Crystal oscillator load capacitance:

0 = external.

1 = internal (value specified by the vendor).

6

XTAL_EN

Crystal oscillator enable:

0 = Crystal driver disabled.

1 = Crystal driver enabled.

5

RSVD

Reserved

4

PP_CLK32K

CLK32K pin driver configuration:

0 = Open drain.

1 = Push pull.

Note that Push-Pull configuration for CLK32K output is optional and not a requirement.

3:0

RSVD

Reserved

Table 8-19 GP_OUT

Address: 0x25

Description: Set General Purpose Output state for sequencing pins EN[12:9]. GPO is enabled through AF_IN_OUT and EN_ALT_F registers.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3

GPO12

EN12 General Purpose Output. Only used when both PWR_EN12 and SLP_EN12 are clear.

0 = EN12 pin driven low.

1 = EN12 pin driven high.

2

GPO11

EN11 General Purpose Output. Only used when both PWR_EN11 and SLP_EN11 are clear.

0 = EN11 pin driven low.

1 = EN11 pin driven high.

1

GPO10

EN10 General Purpose Output. Only used when both PWR_EN10 and SLP_EN10 are clear.

0 = EN10 pin driven low.

1 = EN10 pin driven high.

0

GPO9

EN9 General Purpose Output. Only used when both PWR_EN9 and SLP_EN9 are clear.

0 = EN9 pin driven low.

1 = EN9 pin driven high.
Table 8-20 DEB_IN

Address: 0x26

Description: Debounce configuration for AF input pins.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

DEBOUNCE[3:0]

Debounce value for AF input pins:

0000b = 5 ms

0001b = 10 ms

0010b = 15 ms

0011b = 20 ms

nnnnb = 5(N+1) ms

1111b = 80 ms

3:1

EN_DEB[12:10]

Enable debounce for AF input pins:

0 = debounce disabled.

1 = debounce enabled.

0

RSVD

Reserved

Table 8-21 LP_TTSHLD

Address: 0x27

Description: NPWR_BTN Long Press time threshold configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

LP_TIME_TSHLD

If NPWR_BTN is enabled, this value, in 100 ms increments, determines the minimum duration of the NPWR_BTN pulse to be detected as "Long Press" (shorter is detected as "Short Press")

00h = 100 ms

01h = 200 ms

...

FEh = 25.5 s

FFh = 25.6 s

Table 8-22 CTL_1

Address: 0x28

Description: Interrupt and State SW control.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RSVD

Reserved

3

FORCE_INT (1)

Force NIRQ low:

0 = NIRQ pin controlled by INT_SRCx register faults.

1 = NIRQ pin forced low.

2

FORCE_ACT (2)

Force TPS38700-Q1 active state:

0 (cleared only by I2C writes) = SLEEP pin controls sleep entry/ exit.

1 (set only by HW) = SLEEP is ignored.

1:0

FORCE_SHDN[1:0]

Force TPS38700-Q1 to shutdown state.

With NPWR_BTN disabled (EN_ALT_F.EN_AF12 = 0):

00b = Normal ACT pin control.

01b = Force power-down sequence, then resume normal ACT pin control immediately.

10b = Force power-down sequence, then resume normal ACT pin control after 1 second delay.

11b = Force power-down sequence, then resume normal ACT pin control when ACT = Low or when RTC alarm occurs as per configuration in registers CTL_2, RTC_T, and RTC_A.

With NPWR_BTN enabled (EN_ALT_F.EN_AF12 = 1):

00b = Normal NPWR_BTN pin control.

01b = Force power-down sequence, then move to Sequence 1 immediately (proceed as if ACT = High).

10b = Force power-down sequence, then move to Sequence 1 after 1 second (proceed as if ACT = High). If NPWR_BTN is pressed before 1 second expires, then the TPS38700-Q1 will move to Sequence 1 at that time.

11b = Force power-down sequence, then move to Sequence 1 when RTC alarm occurs as per configuration in registers CTL_2, RTC_T, and RTC_A (proceed as if

ACT = High). If NPWR_BTN is pressed before the RTC alarm, then the TPS38700-Q1 will move to Sequence 1 at that time.
(1) FORCE_INT is used by software for periodic check for internal or external short to VDD on NIRQ pin.
(2) FORCE_ACT is automatically set by HW when entering the Power Up sequence (SEQUENCE 1). As the TPS38700-Q1 performs the power-up sequence, ACT may be undefined. FORCE_ACT being set prevents a bad ACT level from causing a transition directly into SLEEP before the application processor has booted. I2C commands are allowed to clear this bit but not set it.
Table 8-23 CTL_2

Address: 0x29

Description: Miscellaneous configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

RST_DLY[3:0]

Power up sequence: NRST remains asserted until RST_DLY[3:0] after last ENx assert.

0000b = 0.1 ms

0001b = 0.2 ms

0010b = 0.4 ms

0011b = 0.8 ms

0100b = 1.6 ms

0101b = 3.2 ms

0110b = 6.4 ms

0111b = 12.8 ms

1000b = 1 ms

1001b = 2 ms

1010b = 4 ms

1011b = 8 ms

1100b = 16 ms

1101b = 32 ms

1110b = 64 ms

1111b = 128 ms

Power down sequence: NRST asserted within tNRST of ACT= Low.

3

RTC_WAKE

Autonomous RTC wake alarm enable:

0 = Disabled (CTL_1.FORCE_ACT = 0 on RTC alarm).

1 = Enabled (CTL_1.FORCE_ACT = 1 on RTC alarm).

If RTC_T == RTC_A, a wake event is generated which sets INT_SRC1.RTC.

If this bit is enabled, then also CTL_1.FORCE_ACT is set to 1, triggering the automatic exit from SLEEP state to ACTIVE.

2

RTC_PU

Autonomous RTC Power Up from SHDN2 to ACTIVE:

0 = Disabled.

1 = Enabled.

If RTC_T == RTC_A, a power-up event is generated.

1

REQ_PEC

Require PEC byte (valid only if EN_PEC is 1):

0 = missing PEC byte is treated as good PEC.

1 = missing PEC byte is treated as bad PEC, triggering a fault.

0

EN_PEC

Packet Error Checking (PEC):

0 = PEC disabled (Default).

1 = PEC Enabled. Disables support for register address auto-increment.

Table 8-24 TEST_CFG

Address: 0x2A

Description: Built-In Self Test (BIST) execution configuration.

Default: Loaded from NVM (only AT_POR[1:0])

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:3

RSVD

Reserved

2

AT_SHDN

0 = Do not run BIST when exiting Sequence 5 or Sequence 6.

1 = Run BIST when exiting Sequence 5 or Sequence 6 if CTL_1.FORCE_SHDN[1:0] = 00b.

Device ready after tCFG_WB.

This bit cannot be set in OTP.

Always defaults to 0 when loading configuration from OTP.

1:0

AT_POR[1:0]

Run BIST at POR. Device ready after tCFG_WB.

00b = Valid OTP configuration, skip BIST at POR

01b = Corrupt OTP configuration, run BIST at POR.

10b = Corrupt OTP configuration, run BIST at POR.

11b = Valid OTP configuration, run BIST at POR.
Table 8-25 IEN_VENDOR

Address: 0x2B

Description: Vendor Specific Internal Interrupt Enable register.

POR Value: 0x00 or load from NVM.

Access: Read/Write. Read-only if CTL group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

FAULTS[7:0]

Vendor specific internal faults enables.

Table 8-26 SEQ_CFG

Address: 0x30

Description: Sequencing configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:1

RSVD

Reserved

0

SSTEP

Sequencing time slot step size selection for SEQ_USLOT and SEQ_DSLOT:

0 = Time slot step size tSSTEP = 250 μs

1 = Time slot step size tSSTEP= 1000 μs

Table 8-27 SEQ_USLOT

Address: 0x31

Description: Power Up / Sleep Exit sequencing time slot configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

TIME[7:0]

Sets time slot between sequencing points on power-up / sleep-exit:

tUSLOT = SEQ_USLOT.TIME[7:0] × tSSTEP + tSMIN

with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2

For the case where SEQ_CFG.SSTEP = 0, refer to Table 8-28.

For the case where SEQ_CFG.SSTEP = 1, refer to Table 8-29.

Table 8-28 SEQ_CFG.SSTEP = 0

PARAMETER

SYMBOL

MIN (-6%)

TYPICAL

MAX (+6%)

UNIT

Slot step size

tSSTEP

235

250

265

μs

Min slot time (0x00)

tSMIN

117.5

125

132.5

μs

Max slot time (0xFF)

tSMAX

60042.5

63875

67707.5

μs

Table 8-29 SEQ_CFG.SSTEP = 1

PARAMETER

SYMBOL

MIN (-6%)

TYPICAL

MAX (+6%)

UNIT

Slot step size

tSSTEP

940

1000

1060

μs

Min slot time (0x00)

tSMIN

470

500

530

μs

Max slot time (0xFF)

tSMAX

240170

255500

270830

μs

Table 8-30 SEQ_DSLOT

Address: 0x32

Description: Power Down / Sleep Entry sequencing time slot configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

TIME[7:0]

Sets time slot between sequencing points on power-down / sleep-entry:

tDSLOT = SEQ_DSLOT.TIME[7:0] × tSSTEP + tSMIN

with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2

See Table 8-27 for setting details.

Table 8-31 PWR_EN[12:1]

Address: PWR_EN1 (0x33) - PWR_EN12 (0x3E) (Twelve 8-bit registers).

Description: Power Up/ Down sequence definition by assignment of EN[12:1] to one of fifteen time slots.

Slot=1 is the earliest slot that can be selected and it indicates that the ENx pin will toggle in the first SEQ_USLOT.TIME or SEQ_DSLOT.TIME after the triggering event. See Section 8.3.6.9.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

PU[3:0]

Power Up Sequence:

0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states).

1 = ENx pin mapped to first time slot (first up).

15 = ENx pin mapped to last time slot (last up).

3:0

PD[3:0]

Power Down Sequence:

0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states).

1 = ENx pin mapped to first time slot (first down).

15 = ENx pin mapped to last time slot (last down).

Table 8-32 PWR_CLK32OE

Address: 0x3Fh

Description: Power Up/ Down (PU/ PD) sequence assignment of 32 kHz clock output to one of fifteen time slots.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

PU[3:0]

0 = CLK32 not mapped to PU sequence. CLK32 maintains previous state, unless entering BACKUP or FAILSAFE state (CLK32 is pulled low in those states).

1 = Enable CLK32 on first PU time slot.

15 = Enable CLK32 on last PU time slot.

3:0

PD[3:0]

0 = CLK32 not mapped to PD sequence. CLK32 maintains previous state, unless entering BACKUP or FAILSAFE state (CLK32 is pulled low in those states).

1 = Disable CLK32 on first PD time slot.

15 = Disable CLK32 on last PD time slot.

Table 8-33 SLP_EN[12:1]

Address: SLP_EN1 (0x53) - SLP_EN12 (0x5E) (Twelve 8-bit registers).

Description: Sleep Exit/Entry sequence definition by assignment of EN[12:1] to one of fifteen time slots.

Slot=1 is the earliest slot that can be selected and it indicates that the ENx pin will toggle in the first SEQ_USLOT.TIME or SEQ_DSLOT.TIME after the triggering event. See Section 8.3.6.9.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

SLP_EXIT[3:0]

Sleep Exit Sequence:

0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states).

1 = ENx pin mapped to first time slot (first up).

15 = ENx pin mapped to last time slot (last up).

3:0

SLP_ENTRY[3:0]

Sleep Entry Sequence:

0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states).

1 = ENx pin mapped to first time slot (first down).

15 = ENx pin mapped to last time slot (last down).

Table 8-34 SLP_CLK32OE

Address: 0x5F

Description: Sleep Exit/Entry sequence assignment of 32 kHz clock output to one of fifteen time slots.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if SEQ group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:4

SLP_EXIT[3:0]

0 = CLK32 not mapped to Sleep Exit sequence. CLK32 maintains previous state, unless entering BACKUP or FAILSAFE state (CLK32 is pulled low in those states).

1 = Enable CLK32 on first Sleep Exit time slot.

15 = Enable CLK32 on last Sleep Exit time slot.

3:0

SLP_ENTRY[3:0]

0 = CLK32 not mapped to Sleep Entry sequence. CLK32 maintains previous state, unless entering BACKUP or FAILSAFE state (CLK32 is pulled low in those states).

1 = Disable CLK32 on first Sleep Entry time slot.

15 = Disable CLK32 on last Sleep Entry time slot.

Table 8-35 RTC_T[31:0]

Address: RTC_T[31:24] (0x70) - RTC_T[7:0] (0x73) (Four 8-bit registers).

Description: RTC time setting. Although no provision is specified to maintain data coherency across the four registers, it is expected that accessing these registers in a single transaction will guarantee data coherency. RTC_T register values should be written prior to RTC_A values.

POR Value: 0x00000000

Access: Read/Write. Read-only if RTC group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

31:24

RTC_T3

RTC Time Byte 3 Address 0x70

23:16

RTC_T2

RTC Time Byte 2 Address 0x71

15:8

RTC_T1

RTC Time Byte 1 Address 0x72

7:0

RTC_T0

RTC Time Byte 0 Address 0x73

32-bit unsigned value representing 136 years of 1 second ticks since power-on. Can be used to keep POSIX time. Must be set with correct value on each power-up

Table 8-36 RTC_A[31:0]

Address: RTC_A[31:24] (0x74) - RTC_A[7:0] (0x77) (Four 8-bit registers).

Description: RTC alarm setting. Although no provision is specified to maintain data coherency across the four registers, it is expected that accessing these registers in a single transaction will guarantee data coherency.

POR Value: 0xFFFFFFFF

Access: Read/Write. Read-only if RTC group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

31:24

RTC_A3

RTC Alarm Byte 3 Address 0x74

23:16

RTC_A2

RTC Alarm Byte 2 Address 0x75

15:8

RTC_A1

RTC Alarm Byte 1 Address 0x76

7:0

RTC_A0

RTC Alarm Byte 0 Address 0x77

Assert Alarm when RTC_T[31:0]==RTC_A[31:0]. See CTL_2.RTC_WAKE and CTL_2.RTC_PU for wake events.

Table 8-37 WDT_CFG

Address: 0x80

Description: WDT configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if WDT group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:6

WDTEN[1:0]

00b = Watchdog disabled.

01b = On successive expires, first interrupt, then reset, then power-down according to WDT_CFG.PDMD.

10b = On successive expires, first reset, then power-down according to WDT_CFG.PDMD.

11b = Power-down according to WDT_CFG.PDMD on expire.

5

SLP_EN

Automatic disable in sleep mode:

0 = Watchdog disabled automatically in sleep mode.

1 = Watchdog enabled in sleep mode.

4:2

WDTDLY[2:0]

Delay, in number of WDT periods (WDT_CLOSE + WDT_OPEN), from de-assertion of NRST (if exiting SHDN1 or SHDN2 states), or from value written to WDT_CFG.WDTEN[1:0], or from Sleep state exit (if WDT_CFG.SLP_EN=0), to first close window.

000b = 1 WDT period.

111b = 8 WDT periods.

1:0

PDMD[1:0]

Power Down Mode for WDT force power-down.

Value written to CTL_1.FORCE_SHDN[1:0] on WDT power-down event.
Table 8-38 WDT_CLOSE

Address: 0x81

Description: WDT close window configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if WDT group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

CLOSE[7:0]

WDT close window duration:

LSB increment value

1 ms (00h-1Fh)

2 ms (20h-3Fh)

4 ms (40h-FFh)

00h = 1 ms

01h = 2 ms

02h = 3 ms

03h = 4 ms

04h = 5 ms

...

1Dh = 30 ms

1Eh = 31 ms

1Fh = 32 ms

20h = 34 ms

21h = 36 ms

22h = 38 ms

23h = 40 ms

24h = 42 ms

...

3Dh = 92 ms

3Eh = 94 ms

3Fh = 96 ms

40h = 100 ms

41h = 104 ms

42h = 108 ms

43h = 112 ms

44h = 116 ms

...

FDh = 856 ms

FEh = 860 ms

FFh = 864 ms

Table 8-39 WDT_OPEN

Address: 0x82

Description: WDT open window configuration.

POR Value: Loaded from NVM.

Access: Read/Write. Read-only if WDT group is protected.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

OPEN[7:0]

WDT open window duration:

LSB increment value

1 ms (00h-1Fh)

2 ms (20h-3Fh)

4 ms (40h-FFh)

00h = 1 ms

01h = 2 ms

02h = 3 ms

03h = 4 ms

04h = 5 ms

...

1Dh = 30 ms

1Eh = 31 ms

1Fh = 32 ms

20h = 34 ms

21h = 36 ms

22h = 38 ms

23h = 40 ms

24h = 42 ms

...

3Dh = 92 ms

3Eh = 94 ms

3Fh = 96 ms

40h = 100 ms

41h = 104 ms

42h = 108 ms

43h = 112 ms

44h = 116 ms

...

FDh = 856 ms

FEh = 860 ms

FFh = 864 ms

Table 8-40 WDTKEY

Address: 0x83

Description: WDT key to reset.

POR Value: 0x00

Access: Read/Write.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7:0

KEY[7:0]

Watchdog key register.

Table 8-41 PROT1, PROT2

Address: 0xF0, 0xF1

Description: Protection selection registers. In order to write-protect a register group, the host must set the relevant bit in both registers.

POR Value: 0x00

Access: Read/Write.

For security, these registers need to have POR value=0x00 and become read-only once set until power cycle.

Once set to 1, they cannot be cleared to 0 by the host; a power cycle (VDD=0) is required to write different registers configurations.

These registers are cleared also if BIST is executed on exiting Sequence 5 or Sequence 6 (TEST_CFG.AT_SHDN=1).

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

RSVD

Reserved

6

WRK

0 = Working registers are writable.

1 = Writes to working registers are ignored.

5

SEQS

0 = Sleep Sequence registers are writable.

1 = Writes to Sleep Sequence registers are ignored.

4

SEQP

0 = Power Sequence registers are writable.

1 = Writes to Power Sequence registers are ignored.

3

SEQC

0 = Sequence slot configuration registers are writable.

1 = Writes to Sequence slot configuration registers are ignored.

2

WDT

0 = WDT registers are writable.

1 = Writes to WDT registers are ignored.

1

RTC

0 = RTC registers are writable.

1 = Writes to RTC registers are ignored.

0

CTL

0 = Control registers are writable.

1 = Writes to control registers are ignored.
Table 8-42 I2CADDR

Address: 0xF9

Description: I2C address.

POR Value: Loaded from NVM.

Access: Read-Only.

Back to Register Map Table.

BIT

NAME

DESCRIPTION

7

RSVD

Reserved

6:0

ADDR_NVM[6:0]

I2C target device address. Set in NVM.