ZHCSQB8C July   2021  – December 2022 TPS38700-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
      1.      Mechanical, Packaging, and Orderable Information

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8.3.6.1 Sequence 1: Power Up

When NPWR_BTN is not enabled, power-up is controlled by ACT, shown in Figure 8-4.

When ACT is high, the ENx output sequence starts and NRST is de-asserted RST_DLY[3:0] time after the last ENx. The power-up sequence is defined by PWR_ENx registers, for more information see Table 8-31.

Figure 8-4 Power Up with NPWR_BTN Disabled - ACT controlled

When NPWR_BTN is enabled, ACT is used as AUTO/BUTTON power-on strap option. With ACT strapped to VDD, a short push on NPWR_BTN will start the power-up sequence; with ACT strapped to GND, the power-up sequence will automatically start once VDD is valid. From SHDN2 state a short push on NPWR_BTN is always required to start the power-up sequence. See Figure 8-5 for details. When power-up is triggered, the ENx output sequence starts and NRST is de-asserted CTL_2.RST_DLY[3:0] time after the last ENx.

Figure 8-5 Power Up with NPWR_BTN Enabled
Figure 8-6 Power Up from SHDN2 - Software Shutdown with FORCE_SHDN ≠ 00b