ZHCSO95B june   2022  – may 2023 TPS1641

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Shutdown Input (EN/SHDN)
      2. 8.3.2  Overvoltage Protection (OVP)
      3. 8.3.3  Output Slew Rate and Inrush Current Control (dVdt)
      4. 8.3.4  Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
      5. 8.3.5  Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
        1. 8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
      6. 8.3.6  Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
      7. 8.3.7  Fast-Trip and Short-Circuit Protection
      8. 8.3.8  Analog Load Current Monitor (IMON) on the IOCP Pin
      9. 8.3.9  IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
      10. 8.3.10 Thermal Shutdown and Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Overvoltage Setpoints
        2. 9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
        3. 9.2.2.3 Setting the Output Power Limit
        4. 9.2.2.4 Monitoring the Output Current
        5. 9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
    4. 9.4 Best Design Practices
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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7.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP  = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF  CdVdT = Open, PDLY = Open. 
(Allvoltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Enable/SHDN and Vcc Input
tON_DLY Turn on delay with VCC VEN = VENR + 0.1 V , RLOAD = Open 500 µs
tEN_ON_DLY Enable on delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V  , RLOAD = Open 270 µs
tEN_OFF_DLY Enable off delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 1.2 µs
tLOW_SHDN Min low pulse for entering shutdown RLOAD = 100 24 ms
OVP Input
tOVP_ENTRY_DLY OVP entry delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs
tOVP_EXIT_DLY OVP exit delay VOVP = VOVPF - 25 mV to to FLT High 0.6 µs
Over Current Protection and Short-circuit protection
tFASTTRIP_DLY Fast Trip protection delay  IFASTTRIP < IOUT < ISCP to FET OFF 5.65 µs
tSCP_DLY Short-Circuit protection delay IOUT = ISCP + 500 mA to FET OFF 280 ns
Power Limiting
tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 x PLIM, CDLY = 12 nF 6.5 ms
tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 215 µs
tPLIM-DUR PowerLimit Duration 2 x tPDLY s
Current Limiting
tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 12 nF 6.5 ms
tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = OPEN 280 µs
tILIM-DUR Current Limit Duration 2 x tPDLY s
Auto-Retry and Thermal Shutdown
tRETRY Retry Delay 8 x tPDLY s
Output Ramp Control (dVdT)
tdVdT Output Ramp Time CdVdT = Open, VIN = VCC = 24 V 105 µs
IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output
tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 135 ms
tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms