ZHCSA13P November   2008  – February 2021 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图‎
  5. 5 修订历史记录
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 引脚图
    2. 7.2 信号说明
      1. 7.2.1 信号说明
  8. 8 规格
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD 等级 - 汽车
    3. 8.3  ESD 等级 - 商用
    4. 8.4  建议工作条件
    5. 8.5  功耗摘要
      1. 8.5.1 TMS320F2802x/F280200 在 40MHz SYSCLKOUT 下的电流消耗
      2. 8.5.2 TMS320F2802x 在 50MHz SYSCLKOUT 下的电流消耗
      3. 8.5.3 TMS320F2802x 在 60MHz SYSCLKOUT 下的电流消耗
      4. 8.5.4 Reducing Current Consumption
      5. 8.5.5 流耗图（VREG 启用）
    6. 8.6  电气特性
    7. 8.7  热阻特性
      1. 8.7.1 PT 封装
      2. 8.7.2 DA 封装
    8. 8.8  散热设计注意事项
    9. 8.9  无信号缓冲情况下 MCU 与 JTAG 调试探针的连接
    10. 8.10 参数信息
      1. 8.10.1 时序参数符号
      2. 8.10.2 定时参数的通用注释
    11. 8.11 测试负载电路
    12. 8.12 电源时序
      1. 8.12.1 复位 (XRS) 时序要求
      2. 8.12.2 复位 (XRS) 开关特性
    13. 8.13 时钟规范
      1. 8.13.1 器件时钟表
        1. 8.13.1.1 2802x 时钟表和命名规则（40MHz 器件）
        2. 8.13.1.2 2802x 时钟表和命名规则（50MHz 器件）
        3. 8.13.1.3 2802x时钟表和命名规则（60MHz 器件）
        4. 8.13.1.4 器件计时要求/特性
        5. 8.13.1.5 内部零引脚振荡器 (INTOSC1/INTOSC2) 特性
      2. 8.13.2 时钟要求和特性
        1. 8.13.2.1 XCLKIN 定时要求 - PLL 已启用
        2. 8.13.2.2 XCLKIN 时序要求 - PLL 已禁用
        3. 8.13.2.3 XCLKOUT 开关特性（旁路或启用 PLL）
    14. 8.14 闪存定时
      1. 8.14.1 T 温度材料的闪存/OTP 耐久性
      2. 8.14.2 S 温度材料的闪存/OTP 耐久性
      3. 8.14.3 Q 温度材料的闪存/OTP 耐久性
      4. 8.14.4 60MHz SYSCLKOUT 下的闪存参数
      5. 8.14.5 50MHz SYSCLKOUT 上的闪存参数：
      6. 8.14.6 40MHz SYSCLKOUT 上的闪存参数：
      7. 8.14.7 闪存编程/擦除时间
      8. 8.14.8 闪存 / OTP 访问时序
      9. 8.14.9 Flash Data Retention Duration
  9. 9 详细说明
    1. 9.1 Overview
      1. 9.1.1  CPU
      2. 9.1.2  Memory Bus (Harvard Bus Architecture)
      3. 9.1.3  外设总线
      4. 9.1.4  Real-Time JTAG and Analysis
      5. 9.1.5  Flash
      6. 9.1.6  M0，M1 SARAM
      7. 9.1.7  L0 SARAM
      8. 9.1.8  Boot ROM
        1. 9.1.8.1 仿真引导
        2. 9.1.8.2 GetMode
        3. 9.1.8.3 引导加载器使用的外设引脚
      9. 9.1.9  Security
      10. 9.1.10 外设中断扩展 (PIE) 块
      11. 9.1.11 外部中断 (XINT1-XINT3)
      12. 9.1.12 内部零引脚振荡器、振荡器和 PLL
      13. 9.1.13 看门狗
      14. 9.1.14 Peripheral Clocking
      15. 9.1.15 Low-power Modes
      16. 9.1.16 外设帧 0，1，2 (PFn)
      17. 9.1.17 通用输入/输出 (GPIO) 复用器
      18. 9.1.18 32 位 CPU 定时器 (0，1，2)
      19. 9.1.19 Control Peripherals
      20. 9.1.20 串行端口外设
    2. 9.2 Memory Maps
    3. 9.3 Register Maps
    4. 9.4 Device Emulation Registers
    5. 9.5 VREG/BOR/POR
      1. 9.5.1 片载电压稳压器 (VREG)
        1. 9.5.1.1 使用片上 VREG
        2. 9.5.1.2 禁用片载 VREG
      2. 9.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 9.6 系统控制
      1. 9.6.1 内部零引脚振荡器
      2. 9.6.2 Crystal Oscillator Option
      3. 9.6.3 PLL-Based Clock Module
      4. 9.6.4 输入时钟的损耗（NMI 看门狗功能）
      5. 9.6.5 CPU 看门狗模块
    7. 9.7 Low-power Modes Block
    8. 9.8 Interrupts
      1. 9.8.1 External Interrupts
        1. 9.8.1.1 外部中断电子数据/定时
          1. 9.8.1.1.1 External Interrupt Timing Requirements
          2. 9.8.1.1.2 External Interrupt Switching Characteristics
    9. 9.9 外设
      1. 9.9.1  Analog Block
        1. 9.9.1.1 模数转换器 (ADC)
          1. 9.9.1.1.1 特性
          2. 9.9.1.1.2 ADC 转换开始电子数据/定时
            1. 9.9.1.1.2.1 外部 ADC 转换启动开关特性
          3. 9.9.1.1.3 片载模数转换器 (ADC) 电子数据/定时
            1. 9.9.1.1.3.1 ADC Electrical Characteristics
            2. 9.9.1.1.3.2 ADC 电源模式
            3. 9.9.1.1.3.3 内部温度传感器
              1. 9.9.1.1.3.3.1 Temperature Sensor Coefficient
            4. 9.9.1.1.3.4 ADC 加电控制位时序
              1. 9.9.1.1.3.4.1 ADC 加电延迟
            5. 9.9.1.1.3.5 ADC 顺序模式时序和同步模式时序
        2. 9.9.1.2 ADC 多路复用器
        3. 9.9.1.3 比较器块
          1. 9.9.1.3.1 片载比较器 / DAC 电子数据/定时
            1. 9.9.1.3.1.1 Electrical Characteristics of the Comparator/DAC
      2. 9.9.2  详细说明
      3. 9.9.3  Serial Peripheral Interface (SPI) Module
        1. 9.9.3.1 SPI 主模式电气数据/时序
          1. 9.9.3.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 9.9.3.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 9.9.3.2 SPI 从模式电气数据/时序
          1. 9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 9.9.3.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 9.9.4  Serial Communications Interface (SCI) Module
      5. 9.9.5  Inter-Integrated Circuit (I2C)
        1. 9.9.5.1 I2C 电气数据/时序
          1. 9.9.5.1.1 I2C 时序要求
          2. 9.9.5.1.2 I2C 开关特性
      6. 9.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 9.9.6.1 ePWM 电气数据/时序
          1. 9.9.6.1.1 ePWM Timing Requirements
          2. 9.9.6.1.2 ePWM 开关特性
        2. 9.9.6.2 触发区输入时序
          1. 9.9.6.2.1 Trip-Zone Input Timing Requirements
      7. 9.9.7  High-Resolution PWM (HRPWM)
        1. 9.9.7.1 HRPWM 电气数据/时序
          1. 9.9.7.1.1 SYSCLKOUT = 50MHz–60MHz 下的高分辨率 PWM 特性
      8. 9.9.8  Enhanced Capture Module (eCAP1)
        1. 9.9.8.1 eCAP 电气数据/时序
          1. 9.9.8.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 9.9.8.1.2 eCAP 开关特性
      9. 9.9.9  JTAG 端口
      10. 9.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 9.9.10.1 GPIO 电气数据/时序
          1. 9.9.10.1.1 GPIO - 输出时序
            1. 9.9.10.1.1.1 通用输出开关特性
          2. 9.9.10.1.2 GPIO - 输入时序
            1. 9.9.10.1.2.1 通用输入时序要求
          3. 9.9.10.1.3 针对输入信号的采样窗口宽度
          4. 9.9.10.1.4 低功耗唤醒时序
            1. 9.9.10.1.4.1 IDLE Mode Timing Requirements
            2. 9.9.10.1.4.2 IDLE Mode Switching Characteristics
            3. 9.9.10.1.4.3 待机模式时序要求
            4. 9.9.10.1.4.4 待机模式开关特性
            5. 9.9.10.1.4.5 HALT Mode Timing Requirements
            6. 9.9.10.1.4.6 停机模式开关特性
  10. 10应用、实施和布局
    1. 10.1 TI 参考设计
  11. 11器件和文档支持
    1. 11.1 Device and Development Support Tool Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 文档支持
    4. 11.4 支持资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.8 Interrupts

Figure 9-13 shows how the various interrupt sources are multiplexed.

GUID-1DA17302-5BC6-4348-9C0B-BDF006132746-low.gifFigure 9-13 External and PIE Interrupt Sources

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 9-18 shows the interrupts used by 2802x devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.

GUID-36B07754-7CC8-4399-ADE6-3DCC823FA0B0-low.gifFigure 9-14 Multiplexing of Interrupts Using the PIE Block
Table 9-18 PIE MUXed Peripheral Interrupt Vector Table
INTx.8(1)INTx.7INTx.6INTx.5INTx.4INTx.3INTx.2INTx.1
INT1.yWAKEINTTINT0ADCINT9XINT2XINT1ReservedADCINT2ADCINT1
(LPM/WD)(TIMER 0)(ADC)Ext. int. 2Ext. int. 1–(ADC)(ADC)
0xD4E0xD4C0xD4A0xD480xD460xD440xD420xD40
INT2.yReservedReservedReservedReservedEPWM4_TZINTEPWM3_TZINTEPWM2_TZINTEPWM1_TZINT
––––(ePWM4)(ePWM3)(ePWM2)(ePWM1)
0xD5E0xD5C0xD5A0xD580xD560xD540xD520xD50
INT3.yReservedReservedReservedReservedEPWM4_INTEPWM3_INTEPWM2_INTEPWM1_INT
––––(ePWM4)(ePWM3)(ePWM2)(ePWM1)
0xD6E0xD6C0xD6A0xD680xD660xD640xD620xD60
INT4.yReservedReservedReservedReservedReservedReservedReservedECAP1_INT
–––––––(eCAP1)
0xD7E0xD7C0xD7A0xD780xD760xD740xD720xD70
INT5.yReservedReservedReservedReservedReservedReservedReservedReserved
––––––––
0xD8E0xD8C0xD8A0xD880xD860xD840xD820xD80
INT6.yReservedReservedReservedReservedReservedReservedSPITXINTASPIRXINTA
––––––(SPI-A)(SPI-A)
0xD9E0xD9C0xD9A0xD980xD960xD940xD920xD90
INT7.yReservedReservedReservedReservedReservedReservedReservedReserved
––––––––
0xDAE0xDAC0xDAA0xDA80xDA60xDA40xDA20xDA0
INT8.yReservedReservedReservedReservedReservedReservedI2CINT2AI2CINT1A
––––––(I2C-A)(I2C-A)
0xDBE0xDBC0xDBA0xDB80xDB60xDB40xDB20xDB0
INT9.yReservedReservedReservedReservedReservedReservedSCITXINTASCIRXINTA
––––––(SCI-A)(SCI-A)
0xDCE0xDCC0xDCA0xDC80xDC60xDC40xDC20xDC0
INT10.yADCINT8ADCINT7ADCINT6ADCINT5ADCINT4ADCINT3ADCINT2ADCINT1
(ADC)(ADC)(ADC)(ADC)(ADC)(ADC)(ADC)(ADC)
0xDDE0xDDC0xDDA0xDD80xDD60xDD40xDD20xDD0
INT11.yReservedReservedReservedReservedReservedReservedReservedReserved
––––––––
0xDEE0xDEC0xDEA0xDE80xDE60xDE40xDE20xDE0
INT12.yReservedReservedReservedReservedReservedReservedReservedXINT3
–––––––Ext. Int. 3
0xDFE0xDFC0xDFA0xDF80xDF60xDF40xDF20xDF0
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
  1. No peripheral within the group is asserting interrupts.
  2. No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .
Table 9-19 PIE Configuration and Control Registers
NAMEADDRESSSIZE (x16)DESCRIPTION(1)
PIECTRL0x0CE01PIE, Control Register
PIEACK0x0CE11PIE, Acknowledge Register
PIEIER10x0CE21PIE, INT1 Group Enable Register
PIEIFR10x0CE31PIE, INT1 Group Flag Register
PIEIER20x0CE41PIE, INT2 Group Enable Register
PIEIFR20x0CE51PIE, INT2 Group Flag Register
PIEIER30x0CE61PIE, INT3 Group Enable Register
PIEIFR30x0CE71PIE, INT3 Group Flag Register
PIEIER40x0CE81PIE, INT4 Group Enable Register
PIEIFR40x0CE91PIE, INT4 Group Flag Register
PIEIER50x0CEA1PIE, INT5 Group Enable Register
PIEIFR50x0CEB1PIE, INT5 Group Flag Register
PIEIER60x0CEC1PIE, INT6 Group Enable Register
PIEIFR60x0CED1PIE, INT6 Group Flag Register
PIEIER70x0CEE1PIE, INT7 Group Enable Register
PIEIFR70x0CEF1PIE, INT7 Group Flag Register
PIEIER80x0CF01PIE, INT8 Group Enable Register
PIEIFR80x0CF11PIE, INT8 Group Flag Register
PIEIER90x0CF21PIE, INT9 Group Enable Register
PIEIFR90x0CF31PIE, INT9 Group Flag Register
PIEIER100x0CF41PIE, INT10 Group Enable Register
PIEIFR100x0CF51PIE, INT10 Group Flag Register
PIEIER110x0CF61PIE, INT11 Group Enable Register
PIEIFR110x0CF71PIE, INT11 Group Flag Register
PIEIER120x0CF81PIE, INT12 Group Enable Register
PIEIFR120x0CF91PIE, INT12 Group Flag Register
Reserved0x0CFA –
0x0CFF		6Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.