ZHCSUT0D October   2001  – February 2024 TFP410

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 6.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 6.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Universal Graphics Controller Interface Modes
      2. 6.4.2 Data De-skew Feature
      3. 6.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 6.4.4 Device Configuration and I2C RESET Description
      5. 6.4.5 DE Generator
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
    6. 6.6 Register Maps
      1. 6.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 6.6.2  DEV_ID Register (Sub-Address = 03–02) [reset = 0x0410]
      3. 6.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 6.6.4  Reserved Register (Sub-Address = 07–05) [reset = 0x641400]
      5. 6.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xBE]
      6. 6.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 6.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 6.6.8  CFG Register (Sub-Address = 0B)
      9. 6.6.9  RESERVED Register (Sub-Address = 0E–0C) [reset = 0x97D0A9]
      10. 6.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 6.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 6.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 6.6.13 DE_CNT Register (Sub-Address = 37–36) [reset = 0x0000]
      14. 6.6.14 DE_LIN Register (Sub-Address = 39–38) [reset = 0x0000]
      15. 6.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 6.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Data and Control Signals
        2. 7.2.2.2 Configuration Options
        3. 7.2.2.3 Power Supplies Decoupling
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 DVDD
      2. 7.3.2 TVDD
      3. 7.3.3 PVDD
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layer Stack
        2. 7.4.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
        3. 7.4.1.3 DVI Connector
      2. 7.4.2 Layout Example
      3. 7.4.3 TI PowerPAD 64-Pin HTQFP Package
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • PAP|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3.3 Universal Graphics Controller Interface Clock Inputs

The universal graphics controller interface of the TFP410 supports both fully differential and single-ended clock input modes. In the differential clock input mode, the universal graphics controller interface uses the crossover point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0], DE, HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The differential clock input mode is only available in the low-swing mode. In the single-ended clock input mode, the IDCK+ input (Pin 57) should be connected to the single-ended clock source and the IDCK− input (Pin 56) should be tied to GND.

The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit single-edge, input clocking modes. In the 12-bit dual-edge, the 12-bit data is latched on each edge of the input clock. In the 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when EDGE = 1 and the falling edge of the input clock when EDGE = 0.

DKEN and DK[3:1] allow the user to compensate the skew between IDCK± and the pixel data and control signals. See Table 6-10 for details.