ZHCSUT0D October   2001  – February 2024 TFP410

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 6.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 6.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Universal Graphics Controller Interface Modes
      2. 6.4.2 Data De-skew Feature
      3. 6.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 6.4.4 Device Configuration and I2C RESET Description
      5. 6.4.5 DE Generator
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
    6. 6.6 Register Maps
      1. 6.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 6.6.2  DEV_ID Register (Sub-Address = 03–02) [reset = 0x0410]
      3. 6.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 6.6.4  Reserved Register (Sub-Address = 07–05) [reset = 0x641400]
      5. 6.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xBE]
      6. 6.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 6.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 6.6.8  CFG Register (Sub-Address = 0B)
      9. 6.6.9  RESERVED Register (Sub-Address = 0E–0C) [reset = 0x97D0A9]
      10. 6.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 6.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 6.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 6.6.13 DE_CNT Register (Sub-Address = 37–36) [reset = 0x0000]
      14. 6.6.14 DE_LIN Register (Sub-Address = 39–38) [reset = 0x0000]
      15. 6.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 6.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Data and Control Signals
        2. 7.2.2.2 Configuration Options
        3. 7.2.2.3 Power Supplies Decoupling
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 DVDD
      2. 7.3.2 TVDD
      3. 7.3.3 PVDD
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layer Stack
        2. 7.4.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
        3. 7.4.1.3 DVI Connector
      2. 7.4.2 Layout Example
      3. 7.4.3 TI PowerPAD 64-Pin HTQFP Package
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PAP|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Register Maps

The TFP410 is a standard I2C target device. All the registers can be written and read through the I2C interface (unless otherwise specified). The TFP410 target machine supports only byte read and write cycles. Page mode is not supported. The 8-bit binary address of the I2C machine is 0111 A3A2A1X, where A[3:1] are pin programmable or set to 000 by default. The I2C base address of the TFP410 is dependent on A[3:1] (pins 6, 7 and 8 respectively) as shown below.

A[3:1] WRITE ADDRESS
(Hex)		 READ ADDRESS
(Hex)
000 70 71
001 72 73
010 74 75
011 76 77
100 78 79
101 7A 7B
110 7C 7D
111 7E 7F
REGISTER RW SUB-
ADDRESS		 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
VEN_ID R 00 VEN_ID[7:0]
R 01 VEN_ID[15:8]
DEV_ID R 02 DEV_ID[7:0]
R 03 DEV_ID[15:8]
REV_ID R 04 REV_ID[7:0]
RESERVED R 05-07 Reserved
CTL_1_MODE RW 08 RSVD TDIS VEN HEN DSEL BSEL EDGE PD
CTL_2_MODE RW 09 VLOW MSEL TSEL RSEN HTPLG MDI
CTL_3_MODE RW 0A DK DKEN CTL RSVD
CFG R 0B CFG
RESERVED RW 0C-31 Reserved
DE_DLY RW 32 DE_DLY[7:0]
DE_CTL RW 33 RSVD DE_GEN VS_POL HS_POL RSVD DE_DLY[8]
DE_TOP RW 34 RSVD DE_DLY[6:0]
RESERVED RW 35 Reserved
DE_CNT RW 36 DE_CNT[7:0]
RW 37 Reserved DE_CNT[10:8]
DE_LIN RW 38 DE_LIN[7:0]
RW 39 Reserved DE_LIN[10:8]
H_RES R 3A H_RES[7:0]
R 3B Reserved H_RES[10:8]
V_RES R 3C V_RES[7:0]
R 3D Reserved V_RES[10:8]
RESERVED R 3E−FF