SLDS145C October   2001  – December 2014 TFP410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 7.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 7.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Universal Graphics Controller Interface Modes
      2. 7.4.2 Data De-skew Feature
      3. 7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 7.4.4 Device Configuration and I2C RESET Description
      5. 7.4.5 DE Generator
    5. 7.5 Programming
      1. 7.5.1 I2C interface
    6. 7.6 Register Maps
      1. 7.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 7.6.2  DEV_ID Register (Sub-Address = 03-02) [reset = 0x0410]
      3. 7.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 7.6.4  Reserved Register (Sub-Address = 07-05) [reset = 0x641400]
      5. 7.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]
      6. 7.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 7.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 7.6.8  CFG Register (Sub-Address = 0B)
      9. 7.6.9  RESERVED Register (Sub-Address = 0E-0C) [reset = 0x97D0A9]
      10. 7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 7.6.13 DE_CNT Register (Sub-Address = 37-36) [reset = 0x0000]
      14. 7.6.14 DE_LIN Register (Sub-Address = 39-38) [reset = 0x0000]
      15. 7.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 7.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Data and Control Signals
        2. 8.2.2.2 Configuration Options
        3. 8.2.2.3 Power Supplies Decoupling
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 DVDD
    2. 9.2 TVDD
    3. 9.3 PVDD
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      3. 10.1.3 DVI Connector
    2. 10.2 Layout Example
    3. 10.3 TI PowerPAD 64-Pin HTQFP Package
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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1 Features

  • Digital Visual Interface (DVI) Compliant(1)
  • Supports Pixel Rates up to 165 MHz (Including 1080 p and WUXGA at 60 Hz)
  • Universal Graphics Controller Interface
    • 12-Bit, Dual-Edge and 24-Bit, Single-Edge Input Modes
    • Adjustable 1.1 V to 1.8 V and Standard 3.3 V CMOS Input Signal Levels
    • Fully Differential and Single-Ended Input Clocking Modes
    • Standard Intel 12-Bit Digital Video Port Compatible as on Intel™ 81x Chipsets
  • Enhanced PLL Noise Immunity
    • On-Chip Regulators and Bypass Capacitors for Reducing System Costs
  • Enhanced Jitter Performance
    • No HSYNC Jitter Anomaly
    • Negligible Data-Dependent Jitter
  • Programmable Using I2C Serial Interface
  • Monitor Detection Through Hot-Plug and Receiver Detection
  • Single 3.3-V Supply Operation
  • 64-Pin TQFP Using TI’s PowerPAD™ Package
  • TI’s Advanced 0.18-µm EPIC-5™ CMOS Process Technology
  • Pin Compatible With SiI164 DVI Transmitter (1)
(1) The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high-speed digital connection to digital displays and has been adopted by industry-leading PC and consumer electronics manufacturers. The TFP410 is compliant to the DVI Revision 1.0 specification.

2 Applications

  • DVD
  • Blu-ray
  • HD Projectors
  • DVI/HDMI Transmitter(2)(1)
(1) HDMI video-only

3 Description

The TFP410 device is a Texas Instruments PanelBus™ flat-panel display product, part of a comprehensive family of end-to-end DVI 1.0-compliant solutions, targeted at the PC and consumer electronics industry.

The TFP410 device provides a universal interface to allow a glueless connection to most commonly available graphics controllers. Some of the advantages of this universal interface include selectable bus widths, adjustable signal levels, and differential and single-ended clocking. The adjustable 1.1-V to 1.8-V digital interface provides a low-EMI, high-speed bus that connects seamlessly with 12-bit or 24-bit interfaces. The DVI interface supports flat-panel display resolutions up to UXGA at 165 MHz in 24-bit true color pixel format.

The TFP410 device combines PanelBus circuit innovation with TI’s advanced 0.18 μm EPIC-5 CMOS process technology and TI’s ultralow ground inductance PowerPAD package. The result is a compact 64-pin TQFP package providing a reliable, low-current, low-noise, high-speed digital interface solution.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TFP410 HTQFP (64) 10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical HDMI Interface

tfp401_diag_slds145.png

4 Revision History

Changes from B Revision (May 2011) to C Revision

  • Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go