SLLSFV1 March   2025 MCF8329A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Three Phase BLDC Gate Drivers
      2. 6.3.2  Gate Drive Architecture
        1. 6.3.2.1 Dead time and Cross Conduction Prevention
      3. 6.3.3  AVDD Linear Voltage Regulator
      4. 6.3.4  Low-Side Current Sense Amplifier
      5. 6.3.5  Device Interface Modes
        1. 6.3.5.1 Interface - Control and Monitoring
        2. 6.3.5.2 I2C Interface
      6. 6.3.6  Motor Control Input Options
        1. 6.3.6.1 Analog-Mode Motor Control
        2. 6.3.6.2 PWM-Mode Motor Control
        3. 6.3.6.3 Frequency-Mode Motor Control
        4. 6.3.6.4 I2C based Motor Control
        5. 6.3.6.5 Input Control Signal Profiles
          1. 6.3.6.5.1 Linear Control Profiles
          2. 6.3.6.5.2 Staircase Control Profiles
          3. 6.3.6.5.3 Forward-Reverse Profiles
        6. 6.3.6.6 Control Input Transfer Function without Profiler
      7. 6.3.7  Bootstrap Capacitor Initial Charging
      8. 6.3.8  Starting the Motor Under Different Initial Conditions
        1. 6.3.8.1 Case 1 – Motor is Stationary
        2. 6.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 6.3.9  Motor Start Sequence (MSS)
        1. 6.3.9.1 Initial Speed Detect (ISD)
        2. 6.3.9.2 Motor Resynchronization
        3. 6.3.9.3 Reverse Drive
          1. 6.3.9.3.1 Reverse Drive Tuning
        4. 6.3.9.4 Motor Start-up
          1. 6.3.9.4.1 Align
          2. 6.3.9.4.2 Double Align
          3. 6.3.9.4.3 Initial Position Detection (IPD)
            1. 6.3.9.4.3.1 IPD Operation
            2. 6.3.9.4.3.2 IPD Release
            3. 6.3.9.4.3.3 IPD Advance Angle
          4. 6.3.9.4.4 Slow First Cycle Startup
          5. 6.3.9.4.5 Open loop
          6. 6.3.9.4.6 Transition from Open to Closed Loop
      10. 6.3.10 Closed Loop Operation
        1. 6.3.10.1 Closed loop accelerate
        2. 6.3.10.2 Speed PI Control
        3. 6.3.10.3 Current PI Control
        4. 6.3.10.4 Power Loop
        5. 6.3.10.5 Modulation Index Control
      11. 6.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 6.3.12 Flux Weakening Control
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 Dead Time Compensation
      19. 6.3.19 Voltage Sense Scaling
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Recirculation Mode
        3. 6.3.20.3 Low-Side Braking
        4. 6.3.20.4 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG in Open-Loop
        3. 6.3.21.3 FG During Motor Stop
        4. 6.3.21.4 FG Behavior During Fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 6.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 6.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 6.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 6.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 6.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 6.3.23.7  Thermal Shutdown (OTSD)
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 6.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock (MTR_LCK)
          1. 6.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 6.3.23.11 Motor Lock Detection
          1. 6.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 6.3.23.12 MPET Faults
        13. 6.3.23.13 IPD Faults
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 6.5.2 Oscillator Source
        1. 6.5.2.1 External Clock Source
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Operation
        3. 6.6.2.3 I2C Read Operation
        4. 6.6.2.4 Examples of I2C Communication Protocol Packets
        5. 6.6.2.5 Internal Buffers
        6. 6.6.2.6 CRC Byte Calculation
  8. 7 EEPROM (Non-Volatile) Register Map
    1. 7.1 Algorithm_Configuration Registers
    2. 7.2 Fault_Configuration Registers
    3. 7.3 Hardware_Configuration Registers
    4. 7.4 Internal_Algorithm_Configuration Registers
  9. 8 RAM (Volatile) Register Map
    1. 8.1 Fault_Status Registers
    2. 8.2 Algorithm_Control Registers
    3. 8.3 System_Status Registers
    4. 8.4 Device_Control Registers
    5. 8.5 Algorithm_Variables Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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6.5.1 DRVOFF - Gate Driver Shutdown Functionality

When DRVOFF is driven high, the gate driver goes into shutdown. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver output (see Figure 6-47). This pin provides a mechanism for externally monitored faults to disable gate driver by directly bypassing the internal control logic. When the MCF8329A-Q1 detects logic high on the DRVOFF pin, the device disables the gate driver and puts the device into pull down mode (see Figure 6-48). The gate driver shutdown sequence proceeds as shown in Figure 6-48. When the gate driver initiates the shutdown sequence, the active driver pull down is applied at ISINK current for the tSD_SINK_DIG time, after which the gate driver moves to passive pull down mode.

MCF8329A-Q1 DRVOFF Gate Driver Output StateFigure 6-47 DRVOFF Gate Driver Output State
MCF8329A-Q1 Gate Driver Shutdown SequenceFigure 6-48 Gate Driver Shutdown Sequence
Note: Pulling the DRVOFF pin high does not cause the device to enter sleep or standby mode and the digital core is still active. The DRVOFF status is reported on DRV_OFF bit and has a latency of up to 200ms between the pin status change to DRV_OFF bit status update. The DRVOFF is not reported on nFAULT pin, however nFAULT pin can go low if a motor fault happens when DRVOFF goes to logic high during motor operation. When DRVOFF is pulled from high to low, MCF8329A-Q1 execute motor start sequence (with a latency up to 200ms after pulling DRVOFF pin low) as described in Section 6.3.9.