ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
Each PLL supports programmable loop bandwidth from 200 Hz to 1 MHz. The loop filter components, R2, C1, R3, C3, can be configured by programming R67, R68, R69, and R70, respectively, for PLL1 and R82, R83, R84, and R85, respectively, for PLL2. C2 for each PLL is an external component that is added on the LF1 or LF2 pins. When PLL1 and/or PLL2 are configured in the fractional mode, R69.0 and/or R84.0 should be set to 1, respectively, and R118[2-0] and/or R132[2-0] should each be set to 0x7, respectively. When PLL1 and/or PLL2 are configured in the integer mode, R69.0 and/or R84.0 should be set to 0, respectively, and R118[2-0] and/or R132[2-0] should each be set to 0x3 for second-order (NOTE: R69 and R84 should each be set to 0x0) or 0x7 for third-order, respectively. When the PLL1 and/or PLL2's loop bandwidth is desired to be set to 200 Hz, R120.0 and/or R134.0 should be set to 0, respectively. Figure 58 shows the loop filter structure of either PLL.
It is important to set the PLL to best possible bandwidth to minimize output jitter. A high bandwidth (≥ 100 kHz) provides best input signal tracking and is therefore desired with a clean input reference (clock generator mode). A low bandwidth (≤ 1 kHz) is desired if the input signal quality is unknown (jitter cleaner mode). TI provides the WEBENCH Clock Architect that makes it easy to select the right loop filter components.