ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
CMOS Output Divider 0
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:0] | CMOSDIV0[7:0] | RW | 0x00 | Y | CMOS Output Divider 0. The CMOS Divider0, CMOSDIV0, is a 8-bit divider that divides the clock source from the PLL1 LVCMOS Pre-Divider output. The valid values for CMOSDIV0 range from 1 to 256 as shown below. | |
CMOSDIV0 | DIVIDE RATIO | |||||
0 (0x00) | Disabled | |||||
1 (0x01), 2 (0x02), 3 (0x03), 4 (0x04), 5 (0x05) | 6 | |||||
6 (0x06) | 7 | |||||
7 (0x07) | 8 | |||||
... | ||||||
255 (0xFF) | 256 | |||||
Whenever CMOS Divider0 is disabled, by setting CMOSDIV0 to 0, a Software reset should be issued, by setting SWRCMOSCH to 1, after the divider is programmed to a nonzero value. |