ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
In this mode, the GPIO[5:0] pins allow hardware pin configuration of the PLL synthesizer, its input clock selection and output frequency and type selection. I2C is still enabled and the LSB of device address is set to 0x0. The GPIO pins are 2-state and are sampled and latched at POR and the combination selects one of 64 page settings that are predefined in on-chip ROM. In this mode, automatic output divider and PLL post divider synchronization is performed on power-up or upon toggling PDN. Table 15, Table 16, Table 17, Table 18 and Table 19 show the pre-defined ROM configurations according to the GPIO[5:0] pin settings.
Following are the blocks that are configured by the GPIO[5:0] pins.