ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The PLL2_FRACDEN_BY0 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7:0] | PLL2_DEN[7:0] | RW | 0x00 | Y | PLL2 Fractional Divider Denominator Byte 0. Bits 7 to 0. |