ZHCSE36D August   2015  – April 2018 LMK03328

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      LMK03328 简化框图
  4. 修订历史记录
  5. 说明 (续)
  6. 器件比较表
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Thermal Information
    6. 8.6  Electrical Characteristics - Power Supply
    7. 8.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 8.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 8.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 8.10 VCO Characteristics
    11. 8.11 PLL Characteristics
    12. 8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 8.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 8.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 8.15 AC-LVPECL Output Characteristics
    16. 8.16 AC-LVDS Output Characteristics
    17. 8.17 AC-CML Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Power-On/Reset Characteristics
    20. 8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 8.22 Analog Input Characteristics (GPIO[5])
    23. 8.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 8.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 8.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 8.26 Closed-Loop Output Jitter Characteristics
    27. 8.27 PCIe Clock Output Jitter
    28. 8.28 Typical Power Supply Noise Rejection Characteristics
    29. 8.29 Typical Power Supply Noise Rejection Characteristics
    30. 8.30 Typical Closed-Loop Output Spur Characteristics
    31. 8.31 Typical Characteristics
  9. Parameter Measurement Information
    1. 9.1 Test Configurations
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Block-Level Description
      2. 10.3.2 Device Configuration Control
        1. 10.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 10.3.2.1.1 PLL Blocks
          2. 10.3.2.1.2 Output Buffer Auto Mute
          3. 10.3.2.1.3 Input Block
          4. 10.3.2.1.4 Channel Mux
          5. 10.3.2.1.5 Output Divider
          6. 10.3.2.1.6 Output Driver Format
          7. 10.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 10.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 10.3.2.2.1 Device Config Space
          2. 10.3.2.2.2 PLL Blocks
          3. 10.3.2.2.3 Output Buffer Auto Mute
          4. 10.3.2.2.4 Input Block
          5. 10.3.2.2.5 Channel Mux
          6. 10.3.2.2.6 Output Divider
          7. 10.3.2.2.7 Output Driver Format
          8. 10.3.2.2.8 Status MUX, Divider and Slew Rate
        3. 10.3.2.3 Register File Reference Convention
    4. 10.4 Device Functional Modes
      1. 10.4.1  Smart Input MUX
      2. 10.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 10.4.3  Crystal Input Interface (SEC_REF)
      4. 10.4.4  Reference Doubler
      5. 10.4.5  Reference Divider (R)
      6. 10.4.6  Input Divider (M)
      7. 10.4.7  Feedback Divider (N)
      8. 10.4.8  Phase Frequency Detector (PFD)
      9. 10.4.9  Charge Pump
      10. 10.4.10 Loop Filter
      11. 10.4.11 VCO Calibration
      12. 10.4.12 Fractional Circuitry
        1. 10.4.12.1 Programmable Dithering Levels
        2. 10.4.12.2 Programmable Delta Sigma Modulator Order
      13. 10.4.13 Post Divider
      14. 10.4.14 High-Speed Output MUX
      15. 10.4.15 High-Speed Output Divider
      16. 10.4.16 High-Speed Clock Outputs
      17. 10.4.17 Output Synchronization
      18. 10.4.18 Status Outputs
        1. 10.4.18.1 Loss of Reference
        2. 10.4.18.2 Loss of Lock
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 Block Register Write
      3. 10.5.3 Block Register Read
      4. 10.5.4 Write SRAM
      5. 10.5.5 Write EEPROM
      6. 10.5.6 Read SRAM
      7. 10.5.7 Read EEPROM
      8. 10.5.8 Read ROM
      9. 10.5.9 Default Device Configurations in EEPROM and ROM
    6. 10.6 Register Maps
      1. 10.6.1   VNDRID_BY1 Register; R0
      2. 10.6.2   VNDRID_BY0 Register; R1
      3. 10.6.3   PRODID Register; R2
      4. 10.6.4   REVID Register; R3
      5. 10.6.5   PARTID Register; R4
      6. 10.6.6   PINMODE_SW Register; R8
      7. 10.6.7   PINMODE_HW Register; R9
      8. 10.6.8   SLAVEADR Register; R10
      9. 10.6.9   EEREV Register; R11
      10. 10.6.10  DEV_CTL Register; R12
      11. 10.6.11  INT_LIVE Register; R13
      12. 10.6.12  INT_MASK Register; R14
      13. 10.6.13  INT_FLAG_POL Register; R15
      14. 10.6.14  INT_FLAG Register; R16
      15. 10.6.15  INTCTL Register; R17
      16. 10.6.16  OSCCTL2 Register; R18
      17. 10.6.17  STATCTL Register; R19
      18. 10.6.18  MUTELVL1 Register; R20
      19. 10.6.19  MUTELVL2 Register; R21
      20. 10.6.20  OUT_MUTE Register; R22
      21. 10.6.21  STATUS_MUTE Register; R23
      22. 10.6.22  DYN_DLY Register; R24
      23. 10.6.23  REFDETCTL Register; R25
      24. 10.6.24  STAT0_INT Register; R27
      25. 10.6.25  STAT1 Register; R28
      26. 10.6.26  OSCCTL1 Register; R29
      27. 10.6.27  PWDN Register; R30
      28. 10.6.28  OUTCTL_0 Register; R31
      29. 10.6.29  OUTCTL_1 Register; R32
      30. 10.6.30  OUTDIV_0_1 Register; R33
      31. 10.6.31  OUTCTL_2 Register; R34
      32. 10.6.32  OUTCTL_3 Register; R35
      33. 10.6.33  OUTDIV_2_3 Register; R36
      34. 10.6.34  OUTCTL_4 Register; R37
      35. 10.6.35  OUTDIV_4 Register; R38
      36. 10.6.36  OUTCTL_5 Register; R39
      37. 10.6.37  OUTDIV_5 Register; R40
      38. 10.6.38  OUTCTL_6 Register; R41
      39. 10.6.39  OUTDIV_6 Register; R42
      40. 10.6.40  OUTCTL_7 Register; R43
      41. 10.6.41  OUTDIV_7 Register; R44
      42. 10.6.42  CMOSDIVCTRL Register; R45
      43. 10.6.43  CMOSDIV0 Register; R46
      44. 10.6.44  CMOSDIV1 Register; R47
      45. 10.6.45  STATUS_SLEW Register; R49
      46. 10.6.46  IPCLKSEL Register; R50
      47. 10.6.47  IPCLKCTL Register; R51
      48. 10.6.48  PLL1_RDIV Register; R52
      49. 10.6.49  PLL1_MDIV Register; R53
      50. 10.6.50  PLL2_RDIV Register; R54
      51. 10.6.51  PLL2_MDIV Register; R55
      52. 10.6.52  PLL1_CTRL0 Register; R56
      53. 10.6.53  PLL1_CTRL1 Register; R57
      54. 10.6.54  PLL1_NDIV_BY1 Register; R58
      55. 10.6.55  PLL1_NDIV_BY0 Register; R59
      56. 10.6.56  PLL1_FRACNUM_BY2 Register; R60
      57. 10.6.57  PLL1_FRACNUM_BY1 Register; R61
      58. 10.6.58  PLL1_FRACNUM_BY0 Register; R62
      59. 10.6.59  PLL_FRACDEN_BY2 Register; R63
      60. 10.6.60  PLL1_FRACDEN_BY1 Register; R64
      61. 10.6.61  PLL1_FRACDEN_BY0 Register; R65
      62. 10.6.62  PLL1_MASHCTRL Register; R66
      63. 10.6.63  PLL1_LF_R2 Register; R67
      64. 10.6.64  PLL1_LF_C1 Register; R68
      65. 10.6.65  PLL1_LF_R3 Register; R69
      66. 10.6.66  PLL1_LF_C3 Register; R70
      67. 10.6.67  PLL2_CTRL0 Register; R71
      68. 10.6.68  PLL2_CTRL1 Register; R72
      69. 10.6.69  PLL2_NDIV_BY1 Register; R73
      70. 10.6.70  PLL2_NDIV_BY0 Register; R74
      71. 10.6.71  PLL2_FRACNUM_BY2 Register; R75
      72. 10.6.72  PLL2_FRACNUM_BY1 Register; R76
      73. 10.6.73  PLL2_FRACNUM_BY0 Register; R77
      74. 10.6.74  PLL2_FRACDEN_BY2 Register; R78
      75. 10.6.75  PLL2_FRACDEN_BY1 Register; R79
      76. 10.6.76  PLL2_FRACDEN_BY0 Register; R80
      77. 10.6.77  PLL2_MASHCTRL Register; R81
      78. 10.6.78  PLL2_LF_R2 Register; R82
      79. 10.6.79  PLL2_LF_C1 Register; R83
      80. 10.6.80  PLL2_LF_R3 Register; R84
      81. 10.6.81  PLL2_LF_C3 Register; R85
      82. 10.6.82  XO_MARGINING Register; R86
      83. 10.6.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 10.6.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 10.6.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 10.6.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 10.6.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 10.6.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 10.6.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 10.6.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 10.6.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 10.6.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 10.6.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 10.6.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 10.6.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 10.6.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 10.6.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 10.6.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 10.6.99  XO_OFFSET_SW_BY1 Register; R104
      100. 10.6.100 XO_OFFSET_SW_BY0 Register; R105
      101. 10.6.101 PLL1_CTRL2 Register; R117
      102. 10.6.102 PLL1_CTRL3 Register; R118
      103. 10.6.103 PLL1_CALCTRL0 Register; R119
      104. 10.6.104 PLL1_CALCTRL1 Register; R120
      105. 10.6.105 PLL2_CTRL2 Register; R131
      106. 10.6.106 PLL2_CTRL3 Register; R132
      107. 10.6.107 PLL2_CALCTRL0 Register; R133
      108. 10.6.108 PLL2_CALCTRL1 Register; R134
      109. 10.6.109 NVMCNT Register; R136
      110. 10.6.110 NVMCTL Register; R137
      111. 10.6.111 NVMLCRC Register; R138
      112. 10.6.112 MEMADR_BY1 Register; R139
      113. 10.6.113 MEMADR_BY0 Register; R140
      114. 10.6.114 NVMDAT Register; R141
      115. 10.6.115 RAMDAT Register; R142
      116. 10.6.116 ROMDAT Register; R143
      117. 10.6.117 NVMUNLK Register; R144
      118. 10.6.118 REGCOMMIT_PAGE Register; R145
      119. 10.6.119 XOCAPCTRL_BY1 Register; R199
      120. 10.6.120 XOCAPCTRL_BY0 Register; R200
    7. 10.7 EEPROM Map
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Application Block Diagram Examples
      2. 11.2.2 Jitter Considerations in Serdes Systems
      3. 11.2.3 Frequency Margining
        1. 11.2.3.1 Fine Frequency Margining
        2. 11.2.3.2 Coarse Frequency Margining
      4. 11.2.4 Design Requirements
        1. 11.2.4.1 Detailed Design Procedure
          1. 11.2.4.1.1 Device Selection
            1. 11.2.4.1.1.1 Calculation Using LCM
          2. 11.2.4.1.2 Device Configuration
          3. 11.2.4.1.3 PLL Loop Filter Design
            1. 11.2.4.1.3.1 PLL Loop Filter Design
          4. 11.2.4.1.4 PLL and Clock Output Assignment
      5. 11.2.5 Spur Mitigation Techniques
        1. 11.2.5.1 Phase Detector Spurs
        2. 11.2.5.2 Integer Boundary Fractional Spurs
        3. 11.2.5.3 Primary Fractional Spurs
        4. 11.2.5.4 Sub-Fractional Spurs
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Up Sequence
    2. 12.2 Device Power Up Timing
    3. 12.3 Power Down
    4. 12.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.4.1 Mixing Supplies
      2. 12.4.2 Power-On Reset
      3. 12.4.3 Powering Up From Single-Supply Rail
      4. 12.4.4 Powering Up From Split-Supply Rails
      5. 12.4.5 Slow Power-Up Supply Ramp
      6. 12.4.6 Non-Monotonic Power-Up Supply Ramp
      7. 12.4.7 Slow Reference Input Clock Start-Up
    5. 12.5 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ensure Thermal Reliability
      2. 13.1.2 Support for PCB Temperature up to 105°C
    2. 13.2 Layout Example
  14. 14器件和文档支持
    1. 14.1 接收文档更新通知
    2. 14.2 社区资源
    3. 14.3 商标
    4. 14.4 静电放电警告
    5. 14.5 术语表
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Crystal Input Interface (SEC_REF)

The LMK03328 implements an input crystal oscillator circuitry, known as the Pierce oscillator and is shown in Figure 56. It is enabled when R50.7, R50.6, and R29.1 are set to 1, 0, and 1, respectively. The crystal oscillator circuitry includes programmable on-chip capacitances on each leg of the crystal and a damping resistor intended to minimize overdriven condition of the crystal. The recommended oscillation mode of operation for the input crystal is fundamental mode and the recommended type of circuit for the crystal is parallel resonance with low or high pullability. When the secondary reference is set to crystal input, a crystal must be populated and connected to the SECREF_P and SECREF_N pins.

A crystal’s load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters. The LMK03328 has been characterized with 9-pF parallel resonant crystals with maximum motional resistance of 30 Ω and maximum drive level of 300 µW.

The normalized frequency error of the crystal, due to load capacitance mismatch, can be calculated as Equation 4:

Equation 4. LMK03328 eq01_snas668.gif

where

  • CS is the motional capacitance of the crystal
  • C0 is the shunt capacitance of the crystal
  • CL,R is the rated load capacitance for the crystal
  • CL,A is the actual load capacitance in the implemented PCB for the crystal
  • Δƒ is the frequency error of the crystal
  • ƒ is the rated frequency of the crystal.

The first 3 parameters can be obtained from the crystal vendor.

LMK03328 crystal_input_interface_secondary_reference_snas668.gifFigure 56. Crystal Input Interface on Secondary Reference

If reducing frequency error of the crystal is of utmost importance, a crystal with low pullability should be used. If frequency margining or frequency spiking is desired, a crystal with high pullability should be used to ensure that the desired frequency offset is added to the nominal oscillation frequency. A total of ±50-ppm pulling range is obtained with a crystal whose ratio of shunt capacitance to motional capacitance (C0/C1) is no more than 250.

The programmable capacitors on LMK03328 can be tuned from 14 pF to 24 pF in steps of 14 fF using either an analog voltage on GPIO5 in soft pin mode or through I2C in soft pin or hard pin mode. When using crystals with low pullability, the preferred method is to program R86.3 = 1, R86.2 = 0, and program the appropriate binary code to R104 and R105, in this exact order, that sets the required on-chip load capacitance for least frequency error. GPIO4 pin should be tied to VDD and GPIO5 pin should be floating when device is operating in soft pin mode. Table 4 shows the binary code for on-chip load capacitance on each leg of crystal.

When using crystals with high pullability, the same method as above can be repeated for setting a fixed frequency offset to the nominal oscillation frequency according to Equation 4. In case of a closed-loop system where the crystal frequency can be dynamically changed based on a control signal, the LMK03328 should operate in soft pin mode, the R86.3 should be programmed to 0, and the R86.2 should be programmed to 1. The GPIO5 pin is now configured as an 8-level input with a full scale range of 0 V to 1.8 V, and every 200 mV corresponds to a frequency change according to Equation 4. There are three possibilities to enable margining feature with GPIO5:

  • Programming R86.3 = 0 and R86.2 = 1. In this case, status of GPIO4 pin is ignored.
  • When R86.3 = 0 and R86.2 = 0 is programmed, GPIO4 should be tied to GND. Tying GPIO4 to VDD disables GPIO5 for margining purposes and R94 and R95 determine the on-chip load capacitance for the crystal. If any frequency offset is desired at the output, the appropriate binary code should be programmed to R94 and R95.
  • When R86.3 = 1 and R86.2 = 0 is programmed, GPIO4 should be tied to GND. Tying GPIO4 to VDD disables GPIO5 for margining purposes and R104 and R105 determine the on-chip load capacitance for the crystal. If any frequency offset is desired at the output, the appropriate binary code should be programmed to R104 and R105.

There are two possibilities to drive the GPIO5 pin:

  • The first method is to achieve the desired voltage between 0 V to 1.8 V according to Analog Input Characteristics (GPIO[5]). The pulldown resistor value sets the voltage on GPIO[5] pin that falls within one of eight settings whose pre-programmed on-chip crystal load capacitances are set by R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, and R103.
  • The second method is using a low-pass filtered PWM signal to drive the 8-level GPIO5 pin as shown in Figure 57. The PWM signal could be generated from the frequency difference between a highly stable TCXO and the output of LMK03328 that is provided as a feedback into the GPIO5 pin and used to adjust the on-chip load capacitance on the crystal input to reduce frequency errors from the crystal. This is a quick alternative that produces a frequency error at the LMK03328's output and could be acceptable to any application when compared to a full-characterization with a chosen crystal to understand the exact load pulling required to minimize frequency error at the LMK03328's output. More details on frequency margining are provided in Application and Implementation.
LMK03328 crystal_load_capacitance_compensation_pwm_snas668.gifFigure 57. Crystal Load Capacitance Compensation Using PWM Signal

The incremental load capacitance for each step should be programmed to R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, and R103 according to the chosen crystal's trim sensitivity specifications. The least significant bit programmed to any of the XO offset register corresponds to a load capacitance delta of about 0.02 pF on the crystal input pins.

Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to locate the crystal components very close to the SECREF_P and SECREF_N pins to minimize routing distances. Long traces in the oscillator circuit are a very common source of problems. Don’t route other signals across the oscillator circuit, and make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and noise coupling. If drive level of the crystal should be reduced, a damping resistor (less than 500 Ω) should be accommodated in the layout between the crystal leg and SECREF_P pin. Vias in the oscillator circuit are recommended primarily for connections to the ground plane. Don’t share ground connections; instead, make a separate connection to ground for each component that requires grounding. If possible, place multiple vias in parallel for each connection to the ground plane. The layout must be designed to minimize stray capacitance across the crystal to less than 2 pF total under all circumstances to ensure proper crystal oscillation.