ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The 2 PLLs in LMK03328 can be configured to accommodate various input and output frequencies either through I2C programming interface or in the absence of programming, the PLL can be configured by the ROM page, EEPROM page, or register default settings selected through the control pins. The PLLs can be configured by setting each’s Smart Input MUX, Reference Divider, PLL Loop Filter, Feedback Divider, Prescaler Divider, and Output Dividers.
For each PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met when using primary input or secondary input for the reference clock (FREF).
where
The output frequency is related to the PLL/VCO frequency or the reference input frequency (based on the output MUX selection) as given in Equation 2 and Equation 3.
where