Proper PCB design and layout is important in high-current, fast-switching converter circuits (with high current and voltage slew rates) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of the converter depends to a large extent on PCB layout.

Figure 9-29 denotes the high-frequency switching power loops of the LM63460-Q1 power stage. The topological architecture of a buck converter means that particularly high di/dt current flows in the power MOSFETs and input capacitors, and reducing the parasitic inductance by minimizing the effective power loop areas becomes mandatory. For the LM63460-Q1 in particular, note the dual and symmetrical arrangement of the input capacitors based on the VIN and PGND pins located on each side of the IC package. The high-frequency currents are split in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each other, leading to improved EMI performance.

Figure 9-29 Input Current Loops

The following list summarizes the essential guidelines for PCB layout and component placement to optimize DC/DC converter performance, including thermals and EMI signature. Figure 9-30 shows a recommended layout of the LM63460-Q1 with optimized placement and routing of the power-stage and small-signal components.

• Place the input capacitors as close as possible to the input pin pairs [VIN1, PGND1] and [VIN2, PGND2]: The respective VIN and PGND pins pairs are close together (with an NC pin in between to increase clearance), thus simplifying input capacitor placement. The Enhanced HotRod QFN package provides VIN and PGND pins on either side of the package to enable a symmetrical layout that helps to minimize switching noise and EMI.
  • Use low-ESR ceramic capacitors with X7R or X7S dielectric from VIN1 to PGND1 and VIN2 to PGND2. Place an 0402 capacitor close to each pin pair for high-frequency bypass as shown in Figure 9-30. Use an adjacent 1206 or 1210 capacitor on each side for bulk capacitance.
  • Ground return paths for both the input and output capacitors must consist of localized top-side planes that connect to the PGND1 and PGND2 pins.
  • Use a wide polygon plane on a lower PCB layer to connect VIN1 and VIN2 together and to the input supply.
• Use a solid ground plane on the PCB layer beneath the top layer with the IC: This plane acts as a noise shield and a heat dissipation path. Using the PCB layer directly below the IC minimizes the magnetic field associated with the currents in the switching loops, thus reducing parasitic inductance and switch voltage overshoot and ringing. Use numerous thermal vias near PGND1 and PGND2 for heatsinking to the inner ground planes.
• Make the VIN, VOUT, and GND bus connections as wide as possible: These paths must be wide and direct as possible to reduce any voltage drops on the input or output paths of the converter, thus maximizing efficiency.
• Locate the buck inductor close to the SW1, SW2, and SW3 pins: Use a short, wide connection trace from the converter SW pins to the inductor. At the same time, minimize the length (and area) of this high-dv/dt surface to help reduce capacitive coupling and radiated EMI. Connect the dotted terminal of the inductor to the SW pins.
• Place the VCC and BOOT capacitors close to their respective pins: The VCC and BOOT capacitors represent the supplies for the internal low-side and high-side MOSFET gate drivers, respectively, and thus carry high-frequency currents. Locate C_VCC close to the VCC pin and place a GND via at its return terminal to connect to the GND plane and thus back to IC GND at the exposed pad. Connect C_BOOT close to the CBOOT and SW4 pins.
• Place the feedback divider as close as possible to the FB pin: Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This placement reduces the FB trace length and related noise coupling. The FB pin is the input to the voltage-loop error amplifier and represents a high-impedance node sensitive to noise. The connection to V_OUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the switch node) that can capacitively couple into the feedback path of the converter.
• Provide enough PCB area for proper heatsinking: Use sufficient copper area to achieve a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. Provide adequate heatsinking for the LM63460-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad (GND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers preferably with two-ounce copper thickness (and no less than one ounce).