ZHCSLU2B December   2021  – October 2023 LM63460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN/SYNC)
      4. 8.3.4  Frequency Synchronization (EN/SYNC)
      5. 8.3.5  Clock Locking
      6. 8.3.6  Adjustable Switching Frequency (RT)
      7. 8.3.7  Power-Good Monitor (PGOOD)
      8. 8.3.8  Bias Supply Regulator (VCC, BIAS)
      9. 8.3.9  Bootstrap Voltage and UVLO (CBOOT)
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short-Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Automotive Synchronous Buck Regulator at 400 kHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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8.3.3 Precision Enable and Input Voltage UVLO (EN/SYNC)

The EN/SYNC input supports adjustable input undervoltage lockout (UVLO) programmed by resistor values for application-specific power-up and power-down requirements. Also, an external logic signal can be used to drive the EN/SYNC input to toggle the output ON or OFF and for system sequencing or protection.

The LM63460-Q1 enters a low-IQ shutdown mode when EN/SYNC is pulled below 0.4 V. The internal LDO regulator powers off, shutting down the bias currents of the LM63460-Q1. When the EN/SYNC voltage is between the hard shutdown and the precision enable thresholds, the LM63460-Q1 operates in standby mode with the VCC voltage in regulation. After the voltage at EN/SYNC is above VEN-TH, the converter begins to switch normally, provided the input voltage drives the internal VCC above its rising UVLO threshold of 3.6 V (typical).

The EN/SYNC pin cannot be left floating. The simplest way to enable operation is to connect the EN/SYNC pin to VIN, allowing self-start-up of the LM63460-Q1. However, many applications benefit from the use of a divider network from VIN to EN/SYNC as shown in Figure 8-1, which establishes a precision input voltage UVLO. This can be used for sequencing, to prevent re-triggering of the device when used with long input cables, or to reduce the occurrence of deep discharge of a battery power source. Note that the precision enable threshold, VEN-TH, has a 28% hysteresis to prevent ON/OFF re-triggering. An external logic output of another IC can also be used to drive EN/SYNC, allowing system power sequencing.

Calculate the resistor divider values using Equation 2. See Input Voltage UVLO for additional information.

Equation 2. GUID-20211025-SS0I-PHRK-H57T-9NJHQGPLTHF2-low.svg

where

  • VIN(on) is the required input voltage turn-on threshold.

Note that EN/SYNC can also be used as an external synchronization clock input. A blanking time, tB, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. The blanking time is not applied when the converter is in shutdown mode. The blanking time ranges from 4 µs to 28 µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.