ZHCSLU2B December   2021  – October 2023 LM63460-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN/SYNC)
      4. 8.3.4  Frequency Synchronization (EN/SYNC)
      5. 8.3.5  Clock Locking
      6. 8.3.6  Adjustable Switching Frequency (RT)
      7. 8.3.7  Power-Good Monitor (PGOOD)
      8. 8.3.8  Bias Supply Regulator (VCC, BIAS)
      9. 8.3.9  Bootstrap Voltage and UVLO (CBOOT)
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short-Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Automotive Synchronous Buck Regulator at 400 kHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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订购信息

6 Pin Configuration and Functions

GUID-20210623-CA0I-GFKL-V5HK-FVWNRC0RXLKT-low.svg Figure 6-1 22-Pin Enhanced HotRod ™ QFNRYF Package(Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CBOOT 1 P High-side driver supply rail. Connect a 100-nF capacitor between SW and CBOOT. An internal bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low.
NC 2 — No internal connection
BIAS 3 P Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high-quality 0.1-µF to 1-µF capacitor from this pin to GND for improved noise immunity. If the output voltage is above 12 V, connect BIAS to GND.
VCC 4 O Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads. Connect a high-quality 1-µF capacitor from VCC to GND.
FB 5 I Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3-V or 5-V output voltage settings. Connect to a feedback divider tap point to set an adjustable output voltage. Do not float or connect to GND.
PGOOD 6 O Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low, VIN > 1 V.
RT 7 I/O Connect a resistor from RT to GND with a value between 5.76 kΩ and 66.5 kΩ to set the switching frequency between 200 kHz and 2.2 MHz. Do not float or connect directly to GND.
EN/SYNC 8 I Precision enable input. High = on, Low = off. EN/SYNC can be connected to VIN. Precision enable allows this pin to be used as an adjustable input voltage UVLO. See Precision Enable and Input Voltage UVLO (EN). Do not float. EN/SYNC also functions as a synchronization input pin, triggering on the rising edge of the external clock signal. Use a capacitor to AC couple the clock signal to EN/SYNC. When synchronized to an external clock, the converter operates in FPWM mode and disables the PFM light-load mode. See Section 8.3.5.
NC 9 — No internal connection
VIN2 10 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. A low-impedance connection must be provided to VIN1.
NC 11 — No internal connection
PGND2 12 G Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
NC 13 — No internal connection
SW1 14 P Switch node of the converter. Connect to the output inductor.
SW2 15
SW3 16
NC 17 — No internal connection
PGND1 18 G Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
NC 19 — No internal connection
VIN1 20 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. A low-impedance connection must be provided to VIN2.
NC 21 — No internal connection
SW4 22 P Switch node of the converter. Connect to the bootstrap capacitor.
GND – G Exposed pad of the package internally connected to ground. The exposed pad must be connected to the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal impedance. See Layout Guidelines.
(1) P = Power, G = Ground, I = Input, O = Output