ZHCS766A February 2012 – December 2021 INA230
PRODUCTION DATA
The INA230 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the INA230 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a controller, and the devices controlled by the controller are target devices. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions.
To address a specific device, the controller initiates a start condition by pulling the data signal line (SDA) from a high to a low logic level while SCL is high. All target devices on the bus shift in the target address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target device being addressed responds to the controller by generating an Acknowledge bit (ACK) and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an ACK. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.
Once all data have been transferred, the controller generates a stop condition, indicated by pulling SDA from low to high while SCL is high. The INA230 includes a 28-ms timeout on its interface to prevent locking up the bus.