ZHCSI69B june   2018  – september 2020 DS90C189-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Typical Application Diagrams
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
    1.     DS90C189 Pin Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 AEC-Q100 Qualified
      2. 8.3.2 ESD Protection
      3. 8.3.3 Operating Modes
      4. 8.3.4 LVDS Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Single Pixel Input / Single Pixel Output
      3. 8.4.3 Single Pixel Input / Dual Pixel Output
      4. 8.4.4 Pixel Clock Edge Select (RFB)
      5. 8.4.5 Power Management
      6. 8.4.6 Sleep Mode (PDB)
      7. 8.4.7 LVDS Outputs
      8. 8.4.8 LVCMOS Inputs
    5. 8.5 Programming
      1. 8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.5.1.1 Color Mapping Information
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

DS90C189 Pin Descriptions

NAMENO.I/ODESCRIPTION
1.8-V LVCMOS VIDEO INPUTS
IN_[27:21],
IN_[17:14],
IN_[13:9],
IN_[8:1]
IN_[0]		25-19,
10-7,
5-1,
62-55,
53		IData Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control bit.
Includes pull down.
HS,
VS ,
DE		12,
13,
18		IVideo Control Signal Inputs -
HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
IN_CLK6IPixel Input Clock
Includes pull down.
1.8-V LVCMOS CONTROL INPUTS
MODE027IMode Control Input (MODE0) -
0= Single In / Single Out
1= Single In / Dual Out
Includes pull down.
RFB26IRising / Falling Clock Edge Select Input -
0 = Falling Edge
1 = Rising Edge
Includes pull down.
PDB52IPower Down (Sleep) Control Input -
0 = Sleep (Power Down mode)
1 = Device Active (enabled)
Includes pull down.
VODSEL54IVOD Level Select Input -
0 = Low swing
1 = Normal swing
Includes pull down.
N/C14, 15, 17, 29, 51, 63INo Connect Pin – Leave Open
RSVD11IReserved – Tie to Ground.
LVDS OUTPUTS
OA_C+
OA_C-		43
44		OChannel A LVDS Output Clock –
Expects 100 Ω termination.
OA_[0]+,
OA_[0]-		50
49		OChannel A LVDS Output Data –
Expects 100 Ω termination.
OA_[1]+,
OA_[1]-		48
47		OChannel A LVDS Output Data –
Expects 100 Ω termination.
OA_[2]+,
OA_[2]-		46
45		OChannel A LVDS Output Data –
Expects 100 Ω termination.
OA_[3]+,
OA_[3]-		41
42		OChannel A LVDS Output Data –
Expects 100 Ω termination.
OB_C+,
OB_C-		33
34		OChannel B LVDS Output Clock –
Expects 100 Ω termination.
OB_[0]+,
OB_[0]-		39
40		OChannel B LVDS Output Data –
Expects 100 Ω termination.
OB_[1]+,
OB_[1]-		37
38		OChannel B LVDS Output Data –
Expects 100 Ω termination.
OB_[2]+,
OB_[2]-		35
36		OChannel B LVDS Output Data –
Expects 100 Ω termination.
OB_[3]+,
OB_[3]-		30
32		OChannel B LVDS Output Data –
Expects 100 Ω termination.
POWER AND GROUND
VDDTX31PPower supply for LVDS Drivers, 1.8 V.
VDD28, 64PPower supply pin for core, 1.8 V.
VDDP16PPower supply pin for PLL, 1.8 V.
DAPDAPGConnect DAP to Ground plane.