ZHCSI69B june   2018  – september 2020 DS90C189-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Typical Application Diagrams
  6. Revision History
  7. Pin Configuration and Functions
    1.     DS90C189 Pin Descriptions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 AEC-Q100 Qualified
      2. 8.3.2 ESD Protection
      3. 8.3.3 Operating Modes
      4. 8.3.4 LVDS Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Single Pixel Input / Single Pixel Output
      3. 8.4.3 Single Pixel Input / Dual Pixel Output
      4. 8.4.4 Pixel Clock Edge Select (RFB)
      5. 8.4.5 Power Management
      6. 8.4.6 Sleep Mode (PDB)
      7. 8.4.7 LVDS Outputs
      8. 8.4.8 LVCMOS Inputs
    5. 8.5 Programming
      1. 8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.5.1.1 Color Mapping Information
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Switching Characteristics

Over recommended operating supply and temperature ranges unlessotherwise specified.
PARAMETERMINTYPMAXUNIT
TSTCIN_n Setup to IN_CLKSee Figure 7-60ns
THTCIN_n Hold from IN_CLKSee Figure 7-62.5ns
LLHTLVDS Low-to-High Transition Time
See Figure 7-4
0.33ns
LHLTLVDS High-to-Low Transition Time
See Figure 7-4
0.33ns
TBITLVDS Output Bit WidthMODE0 = GND1/7 TCIPns
MODE0 = VDD2/7 TCIPns
TPPOS0Transmitter Output Pulse Positions Normalized for Bit 0See Figure 7-91UI
TPPOS1Transmitter Output Pulse Positions Normalized for Bit 1See Figure 7-92UI
TPPOS2Transmitter Output Pulse Positions Normalized for Bit 2See Figure 7-93UI
TPPOS3Transmitter Output Pulse Positions Normalized for Bit 3See Figure 7-94UI
TPPOS4Transmitter Output Pulse Positions Normalized for Bit 4See Figure 7-95UI
TPPOS5Transmitter Output Pulse Positions Normalized for Bit 5See Figure 7-96UI
TPPOS6Transmitter Output Pulse Positions Normalized for Bit 6See Figure 7-97UI
Δ_TPPOSVariation in Transmitter Pulse Position (Bit 6 — Bit 0)See Figure 7-9±0.06UI
TCCSLVDS Channel to Channel Skew110ps
TJCCJitter Cycle-to-CycleMODE0 = GND,
f = 105 MHz
0.176UI
TPLLSPhase Lock Loop Set (Enable Time)See Figure 7-71ms
TPDDPowerdown DelaySee Figure 7-8100ns
TSDLatency DelayMODE0 = GND
See Figure 7-11
2*TCIP + 10.542*TCIP + 19.38ns
TLATLatency Delay for Single Pixel In / Dual Pixel Out ModeMODE0 = VDD
See Figure 7-10
9*TCIP + 4.19ns