ZHCSKS2E april   2020  – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
        2. 6.3.2.2 DDRSS Mapping
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
        2. 6.3.9.2 MAIN Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW5G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
        2. 6.3.21.2 MCU Domain
      22. 6.3.22 MCASP
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 DMTIMER
        1. 6.3.23.1 MAIN Domain
        2. 6.3.23.2 MCU Domain
      24. 6.3.24 Emulation and Debug
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 System and Miscellaneous
        1. 6.3.25.1 Boot Mode Configuration
          1. 6.3.25.1.1 MAIN Domain
          2. 6.3.25.1.2 MCU Domain
        2. 6.3.25.2 Clock
          1. 6.3.25.2.1 MAIN Domain
          2. 6.3.25.2.2 WKUP Domain
        3. 6.3.25.3 System
          1. 6.3.25.3.1 MAIN Domain
          2. 6.3.25.3.2 WKUP Domain
          3. 6.3.25.3.3 VMON
        4. 6.3.25.4 EFUSE
      26. 6.3.26 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Power-On-Hours (POH)
    5. 7.5 Operating Performance Points
    6. 7.6 Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  ADC12BT Electrical Characteristics
      7. 7.6.7  LVCMOS Electrical Characteristics
      8. 7.6.8  USB2PHY Electrical Characteristics
      9. 7.6.9  SERDES Electrical Characteristics
      10. 7.6.10 DDR Electrical Characteristics
    7. 7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8 Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameters and Information
      2. 7.9.2 Power Supply Sequencing
        1. 7.9.2.1 Power Supply Slew Rate Requirement
        2. 7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.9.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing
        6. 7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.9.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.9.3 System Timing
        1. 7.9.3.1 Reset Timing
        2. 7.9.3.2 Safety Signal Timing
        3. 7.9.3.3 Clock Timing
      4. 7.9.4 Clock Specifications
        1. 7.9.4.1 Input Clocks / Oscillators
          1. 7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.9.4.1.1.1 Load Capacitance
            2. 7.9.4.1.1.2 Shunt Capacitance
          2. 7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.9.4.1.3.1 Load Capacitance
            2. 7.9.4.1.3.2 Shunt Capacitance
          4. 7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.9.4.1.5 Auxiliary OSC1 Not Used
          6. 7.9.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 7.9.4.1.7 WKUP_LF_CLKIN Not Used
        2. 7.9.4.2 Output Clocks
        3. 7.9.4.3 PLLs
        4. 7.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 7.9.4.5 Interface Clock Specifications
          1. 7.9.4.5.1 Interface Clock Terminology
          2. 7.9.4.5.2 Interface Clock Frequency
      5. 7.9.5 Peripherals
        1. 7.9.5.1  ATL
          1. 7.9.5.1.1 ATL_PCLK Timing Requirements
          2. 7.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.9.5.2  CPSW2G
          1. 7.9.5.2.1 CPSW2G RMII Timings
            1. 7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 7.9.5.2.2 CPSW2G RGMII Timings
            1. 7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 7.9.5.3  CPSW5G
          1. 7.9.5.3.1 CPSW5G MDIO Interface Timings
          2. 7.9.5.3.2 CPSW5G RMII Timings
            1. 7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.9.5.3.3 CPSW5G RGMII Timings
            1. 7.9.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 7.9.5.4  DDRSS
        5. 7.9.5.5  ECAP
          1. 7.9.5.5.1 Timing Requirements for ECAP
          2. 7.9.5.5.2 Switching Characteristics for ECAP
        6. 7.9.5.6  EPWM
          1. 7.9.5.6.1 Timing Requirements for EPWM
          2. 7.9.5.6.2 Switching Characteristics for EPWM
        7. 7.9.5.7  EQEP
          1. 7.9.5.7.1 Timing Requirements for EQEP
          2. 7.9.5.7.2 Switching Characteristics for EQEP
        8. 7.9.5.8  GPIO
        9. 7.9.5.9  GPMC
          1. 7.9.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.9.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.9.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.9.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 7.9.5.10 HyperBus
          1. 7.9.5.10.1 Timing Requirements for HyperBus Initialization
          2. 7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 7.9.5.11 I2C
        12. 7.9.5.12 I3C
        13. 7.9.5.13 MCAN
        14. 7.9.5.14 MCASP
          1. 7.9.5.14.1 Timing Requirements for MCASP
        15. 7.9.5.15 MCSPI
          1. 7.9.5.15.1 MCSPI — Controller Mode
          2. 7.9.5.15.2 MCSPI — Peripheral Mode
        16. 7.9.5.16 eMMC/SD/SDIO
          1. 7.9.5.16.1 MMCSD0 - eMMC Interface
            1. 7.9.5.16.1.1 Legacy SDR Mode
            2. 7.9.5.16.1.2 High Speed SDR Mode
            3. 7.9.5.16.1.3 High Speed DDR Mode
            4. 7.9.5.16.1.4 HS200 Mode
            5. 7.9.5.16.1.5 HS400 Mode
          2. 7.9.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 7.9.5.16.2.1 Default speed Mode
            2. 7.9.5.16.2.2 High Speed Mode
            3. 7.9.5.16.2.3 UHS–I SDR12 Mode
            4. 7.9.5.16.2.4 UHS–I SDR25 Mode
            5. 7.9.5.16.2.5 UHS–I SDR50 Mode
            6. 7.9.5.16.2.6 UHS–I DDR50 Mode
            7. 7.9.5.16.2.7 UHS–I SDR104 Mode
        17. 7.9.5.17 NAVSS
          1. 7.9.5.17.1 Timing Requirements for CPTS Input
          2. 7.9.5.17.2 Switching Characteristics for CPTS Output
        18. 7.9.5.18 OSPI
          1. 7.9.5.18.1 OSPI With Data Training
            1. 7.9.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 7.9.5.18.2 OSPI Without Data Training
            1. 7.9.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.9.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.9.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.9.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 7.9.5.19 PCIE
        20. 7.9.5.20 Timers
          1. 7.9.5.20.1 Timing Requirements for Timers
          2. 7.9.5.20.2 Switching Characteristics for Timers
        21. 7.9.5.21 UART
          1. 7.9.5.21.1 UART Timing Requirements
          2. 7.9.5.21.2 UART Switching Characteristics
        22. 7.9.5.22 USB
      6. 7.9.6 Emulation and Debug
        1. 7.9.6.1 Debug Trace
        2. 7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 7.9.6.2.1 JTAG Electrical Data and Timing
            1. 7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
    3. 8.3 Other Subsystems
      1. 8.3.1 MSMC
      2. 8.3.2 NAVSS
        1. 8.3.2.1 NAVSS0
        2. 8.3.2.2 MCU_NAVSS
      3. 8.3.3 PDMA Controller
      4. 8.3.4 Peripherals
        1. 8.3.4.1  ADC
        2. 8.3.4.2  ATL
        3. 8.3.4.3  CPSW2G
        4. 8.3.4.4  CPSW5G
        5. 8.3.4.5  DCC
        6. 8.3.4.6  DDRSS
        7. 8.3.4.7  ECAP
        8. 8.3.4.8  EPWM
        9. 8.3.4.9  ELM
        10. 8.3.4.10 ESM
        11. 8.3.4.11 EQEP
        12. 8.3.4.12 GPIO
        13. 8.3.4.13 GPMC
        14. 8.3.4.14 Hyperbus
        15. 8.3.4.15 I2C
        16. 8.3.4.16 I3C
        17. 8.3.4.17 MCAN
        18. 8.3.4.18 MCASP
        19. 8.3.4.19 MCRC Controller
        20. 8.3.4.20 MCSPI
        21. 8.3.4.21 MMC/SD
        22. 8.3.4.22 OSPI
        23. 8.3.4.23 PCIE
        24. 8.3.4.24 SerDes
        25. 8.3.4.25 WWDT
        26. 8.3.4.26 Timers
        27. 8.3.4.27 UART
        28. 8.3.4.28 USB
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 USB VBUS Design Guidelines
      4. 9.3.4 System Power Supply Monitor Design Guidelines
      5. 9.3.5 High Speed Differential Signal Routing Guidance
      6. 9.3.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALM|433
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4 Pin Multiplexing

Note:

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

Table 6-106, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing.

Note:

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

Note:

Table 6-106, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the device TRM.

Note:

The PRU contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU chapter in the device TRM.

For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.

Table 6-106 Pin Multiplexing
ADDRESS
OFFSET		REGISTER NAMEBALL NUMBERMUXMODE[15:0] SETTINGS
01234567891011121314Bootstrap
0x1C000WKUP_PADCONFIG_0 B6MCU_OSPI0_CLKMCU_HYPERBUS0_CKWKUP_GPIO0_16
0x1C000PADCONFIG_0 U6EXTINTnGPIO0_0
0x1C004WKUP_PADCONFIG_1 C8MCU_OSPI0_LBCLKOMCU_HYPERBUS0_CKnWKUP_GPIO0_17
0x1C004PADCONFIG_1 AA17RMII1_RXD0RGMII1_RD0RMII1_RXD0MCAN14_TXGPIO0_2TRC_DATA9UART5_TXDMCASP1_AXR3GPMC0_AD0
0x1C008PADCONFIG_2 Y15RMII1_RXD1RGMII1_RD1RMII1_RXD1MCAN14_RXGPIO0_3EHRPWM_TZn_IN2TRC_DATA8UART5_RXDMCASP1_AXR2GPMC0_AD1
0x1C008WKUP_PADCONFIG_2 B7MCU_OSPI0_DQSMCU_HYPERBUS0_RWDSWKUP_GPIO0_18
0x1C00CPADCONFIG_3 AA20RMII1_CRS_DVRGMII1_RD2RMII1_CRS_DVGPIO0_4EHRPWM2_BTRC_DATA7UART4_TXDMCASP1_AXR1GPMC0_AD2
0x1C00CWKUP_PADCONFIG_3 D8MCU_OSPI0_D0MCU_HYPERBUS0_DQ0WKUP_GPIO0_19BOOTMODE00
0x1C010PADCONFIG_4 Y17RMII1_RX_ERRGMII1_RD3RMII1_RX_ERGPIO0_5EHRPWM2_ATRC_DATA6UART6_TXDMCASP1_AXR0GPMC0_AD3
0x1C010WKUP_PADCONFIG_4 C7MCU_OSPI0_D1MCU_HYPERBUS0_DQ1WKUP_GPIO0_20BOOTMODE01
0x1C014WKUP_PADCONFIG_5 C5MCU_OSPI0_D2MCU_HYPERBUS0_DQ2WKUP_GPIO0_21
0x1C014PADCONFIG_5 Y16RMII1_TXD0RGMII1_RX_CTLRMII1_TXD0GPIO0_6EHRPWM0_SYNCOTRC_CTLUART6_RXDMCASP0_AFSXGPMC0_AD4
0x1C018WKUP_PADCONFIG_6 A5MCU_OSPI0_D3MCU_HYPERBUS0_DQ3WKUP_GPIO0_22
0x1C018PADCONFIG_6 V17RMII1_TX_ENRGMII4_RXCRMII1_TX_ENGPIO0_7EQEP2_AUART9_TXDMCASP0_AXR8I2C1_SCLGPMC0_AD5
0x1C01CPADCONFIG_7 AA19RMII1_TXD1RGMII1_RXCRMII1_TXD1GPIO0_8EHRPWM_TZn_IN1TRC_DATA5UART9_RXDMCASP0_AXR3I2C1_SDAGPMC0_AD6
0x1C01CWKUP_PADCONFIG_7 A6MCU_OSPI0_D4MCU_HYPERBUS0_DQ4WKUP_GPIO0_23BOOTMODE02
0x1C020WKUP_PADCONFIG_8 B8MCU_OSPI0_D5MCU_HYPERBUS0_DQ5WKUP_GPIO0_24BOOTMODE03
0x1C020PADCONFIG_8 V18MCAN0_TXRGMII4_RD0MCAN0_TXGPIO0_9EQEP2_BGPMC0_A1MCASP0_AXR9AUDIO_EXT_REFCLK0
0x1C024PADCONFIG_9 V20MCAN0_RXRGMII4_RD1MCAN0_RXGPIO0_10EQEP2_SGPMC0_A2MCASP0_AXR10
0x1C024WKUP_PADCONFIG_9 A8MCU_OSPI0_D6MCU_HYPERBUS0_DQ6WKUP_GPIO0_25
0x1C028PADCONFIG_10 W21MCAN1_TXRGMII2_TXCRMII2_TX_ENMCAN1_TXGPIO0_11SPI6_CS0EHRPWM_SOCAGPMC0_A3MCASP0_AXR11
0x1C028WKUP_PADCONFIG_10 A7MCU_OSPI0_D7MCU_HYPERBUS0_DQ7WKUP_GPIO0_26
0x1C02CPADCONFIG_11 V16MCAN1_RXRGMII4_RD2RMII2_TXD1MCAN1_RXGPIO0_12SPI6_CS1EQEP2_IGPMC0_AD7UART6_CTSnMCASP0_AXR12OBSCLK1
0x1C02CWKUP_PADCONFIG_11 D6MCU_OSPI0_CSn0MCU_HYPERBUS0_CSn0WKUP_GPIO0_27
0x1C030WKUP_PADCONFIG_12 D7MCU_OSPI0_CSn1MCU_HYPERBUS0_RESETnWKUP_GPIO0_28
0x1C030PADCONFIG_12 Y18MCAN2_TXRGMII1_TD0RMII4_RXD0MCAN2_TXGPIO0_13SPI5_CS3EHRPWM1_ATRC_DATA3UART3_RXDMCASP1_AFSXUART9_CTSnGPMC0_AD8
0x1C034PADCONFIG_13 Y19MCAN2_RXRGMII1_TD1RMII4_RXD1MCAN2_RXGPIO0_14SPI5_CS2EHRPWM0_BTRC_DATA2UART3_TXDMCASP1_ACLKXUART9_RTSnGPMC0_AD9
0x1C038PADCONFIG_14 Y21MCAN3_TXRGMII1_TD2RMII4_CRS_DVMCAN3_TXGPIO0_15SPI5_D0EHRPWM0_ATRC_DATA1MCASP0_AXR1GPMC0_AD10
0x1C038WKUP_PADCONFIG_14 C6MCU_OSPI0_CSn2MCU_OSPI0_CSn2MCU_HYPERBUS0_RESETOnMCU_HYPERBUS0_WPnMCU_HYPERBUS0_CSn1MCU_OSPI0_RESET_OUT0WKUP_GPIO0_30
0x1C03CWKUP_PADCONFIG_15 D5MCU_OSPI0_CSn3MCU_OSPI0_CSn3MCU_HYPERBUS0_INTnMCU_HYPERBUS0_WPnMCU_OSPI0_RESET_OUT1MCU_OSPI0_ECC_FAILWKUP_GPIO0_31
0x1C03CPADCONFIG_15 W16MCAN3_RXRGMII1_TD3RMII4_RX_ERMCAN3_RXGPIO0_16SPI5_CS0EHRPWM_TZn_IN0TRC_DATA0GPMC0_A4MCASP0_AXR0SYNC2_OUT
0x1C040PADCONFIG_16 W15MCAN4_TXRGMII1_TX_CTLRMII4_TXD0MCAN4_TXGPIO0_17SPI5_CLKEHRPWM0_SYNCITRC_CLKI2C2_SCLMCASP0_ACLKXGPMC0_AD11
0x1C044PADCONFIG_17 Y20MCAN4_RXRGMII1_TXCRMII4_TX_ENMCAN4_RXGPIO0_18SPI5_D1EHRPWM1_BTRC_DATA4I2C2_SDAMCASP0_AXR2GPMC0_AD12
0x1C048PADCONFIG_18 V21MCAN5_TXRGMII3_RXCRMII4_TXD1MCAN5_TXGPIO0_19SPI5_CS1EHRPWM4_BTRC_DATA17UART6_RTSnMCASP0_AXR7GPMC0_DIRSYNC3_OUT
0x1C04CPADCONFIG_19 V19MCAN5_RXRGMII3_RD0RMII3_RXD0MCAN5_RXGPIO0_20I2C3_SCLEHRPWM_TZn_IN5TRC_DATA21GPMC0_A5MCASP1_AXR7
0x1C050PADCONFIG_20 T13MCAN6_TXRGMII3_RD1RMII3_RXD1MCAN6_TXGPIO0_21I2C3_SDAEHRPWM5_BTRC_DATA20GPMC0_A6MCASP1_AXR6
0x1C054PADCONFIG_21 U14MCAN6_RXRGMII3_RD2RMII3_CRS_DVMCAN6_RXGPIO0_22EHRPWM5_ATRC_DATA19MCASP1_AXR5GPMC0_AD13
0x1C058PADCONFIG_22 U16MCAN7_TXRGMII3_RD3RMII3_RX_ERMCAN7_TXGPIO0_23SPI3_CS0EHRPWM_TZn_IN4TRC_DATA18MCASP1_AXR4GPMC0_AD14
0x1C05CPADCONFIG_23 U15MCAN7_RXRGMII3_RX_CTLRMII3_TXD0MCAN7_RXGPIO0_24SPI3_CS1EHRPWM3_ATRC_DATA11MCASP0_AFSRGPMC0_AD15
0x1C060PADCONFIG_24 T15MCAN8_TXGPMC0_A7RGMII3_TD0RMII3_TX_ENMCAN8_TXGPIO0_25SPI3_CS2EHRPWM_TZn_IN3TRC_DATA15UART3_CTSnMCASP0_AXR5UART0_DCDn
0x1C064PADCONFIG_25 U19MCAN8_RXRGMII3_TD1RMII3_TXD1MCAN8_RXGPIO0_26SPI3_CS3EHRPWM3_SYNCOTRC_DATA14UART3_RTSnMCASP0_AXR4GPMC0_A8UART0_DSRn
0x1C068WKUP_PADCONFIG_26 D11MCU_RGMII1_TX_CTLMCU_RMII1_CRS_DVWKUP_GPIO0_29
0x1C068PADCONFIG_26 T14MCAN9_TXRGMII3_TD2MCAN9_TXGPIO0_27SPI3_CLKEHRPWM3_SYNCITRC_DATA13MCASP1_AFSRGPMC0_A9MCASP1_AXR10
0x1C06CWKUP_PADCONFIG_27 A11MCU_RGMII1_RX_CTLMCU_RMII1_RX_ERWKUP_GPIO0_43
0x1C06CPADCONFIG_27 U18MCAN9_RXRGMII3_TD3MCAN9_RXGPIO0_28SPI3_D0EHRPWM3_BTRC_DATA12MCASP1_ACLKRGPMC0_A10MCASP1_AXR11
0x1C070WKUP_PADCONFIG_28 C12MCU_RGMII1_TD3MCU_TIMER_IO2MCU_ADC_EXT_TRIGGER0WKUP_GPIO0_44
0x1C070PADCONFIG_28 U17MCAN10_TXRGMII3_TX_CTLMCAN10_TXGPIO0_29SPI3_D1EHRPWM_SOCBTRC_DATA10UART2_CTSnMCASP0_ACLKRGPMC0_WAIT1GPMC0_A22
0x1C074PADCONFIG_29 U20MCAN10_RXRGMII3_TXCMCAN10_RXGPIO0_30SPI2_CLKEHRPWM4_ATRC_DATA16UART2_RTSnMCASP0_AXR6GPMC0_BE0n_CLEGPMC0_A16
0x1C074WKUP_PADCONFIG_29 B12MCU_RGMII1_TD2MCU_TIMER_IO3MCU_ADC_EXT_TRIGGER1WKUP_GPIO0_45
0x1C078WKUP_PADCONFIG_30 B11MCU_RGMII1_TD1MCU_RMII1_TXD1WKUP_GPIO0_46
0x1C078PADCONFIG_30 Y14MCAN11_TXRGMII2_RXCMCAN11_TXGPIO0_31SPI2_CS0EQEP0_ASPI0_CS2UART3_RXDMCASP0_AXR13GPMC0_A11UART0_DTRn
0x1C07CPADCONFIG_31 Y13MCAN11_RXRGMII2_RD0MCAN11_RXGPIO0_32SPI2_CS1EQEP0_BUART3_TXDMCASP0_AXR14GPMC0_A12UART0_RIn
0x1C07CWKUP_PADCONFIG_31 D10MCU_RGMII1_TD0MCU_RMII1_TXD0WKUP_GPIO0_47
0x1C080PADCONFIG_32 AA15MCAN12_TXRGMII2_RD1MCAN12_TXGPIO0_33SPI2_CS2EQEP1_AI2C6_SCLUART2_RXDMCASP0_AXR15GPMC0_BE1nGPMC0_A17
0x1C080WKUP_PADCONFIG_32 A12MCU_RGMII1_TXCMCU_RMII1_TX_ENWKUP_GPIO0_48
0x1C084WKUP_PADCONFIG_33 B10MCU_RGMII1_RXCMCU_RMII1_REF_CLKWKUP_GPIO0_49
0x1C084PADCONFIG_33 AA14MCAN12_RXRGMII2_RD2MCAN12_RXGPIO0_34SPI2_CS3EQEP1_BI2C6_SDAUART2_TXDMCASP1_AXR8I3C0_SDAPULLENGPMC0_A18
0x1C088PADCONFIG_34 AA18MCAN13_TXRGMII2_RD3GPMC0_WPnMCAN13_TXGPIO0_35SPI2_D0EQEP0_SI2C5_SCLUART8_CTSnMCASP1_AXR9I3C0_SCLGPMC0_A19
0x1C088WKUP_PADCONFIG_34 C10MCU_RGMII1_RD3MCU_TIMER_IO4WKUP_GPIO0_50
0x1C08CPADCONFIG_35 AA16MCAN13_RXRGMII2_RX_CTLGPMC0_CSn3MCAN13_RXGPIO0_36SPI2_D1EQEP0_II2C5_SDAUART8_RTSnMCASP2_AXR0I3C0_SDAGPMC0_A20
0x1C08CWKUP_PADCONFIG_35 A10MCU_RGMII1_RD2MCU_TIMER_IO5WKUP_GPIO0_51
0x1C090WKUP_PADCONFIG_36 B9MCU_RGMII1_RD1MCU_RMII1_RXD1WKUP_GPIO0_52
0x1C090PADCONFIG_36 W17MCAN15_TXRGMII2_TD0RMII2_RXD0GPIO0_37SPI6_CS2EQEP1_SMCAN15_TXGPMC0_CSn2MCASP2_AXR1GPMC0_A0GPMC0_A21
0x1C094PADCONFIG_37 W20MCAN15_RXRGMII2_TD1RMII2_RXD1GPIO0_38SPI6_CS3EQEP1_IMCAN15_RXMCASP2_AXR2GPMC0_A15GPMC0_ADVn_ALE
0x1C094WKUP_PADCONFIG_37 A9MCU_RGMII1_RD0MCU_RMII1_RXD0WKUP_GPIO0_53
0x1C098PADCONFIG_38 V14UART2_RXDRGMII2_TD2RMII2_CRS_DVGPIO0_39SPI6_CLKGPMC0_CLKOUTGPMC0_FCLK_MUXUART2_RXDMCASP2_AXR3OBSCLK2
0x1C098WKUP_PADCONFIG_38 C9MCU_MDIO0_MDIOWKUP_GPIO0_54
0x1C09CPADCONFIG_39 V13UART2_TXDRGMII2_TD3RMII2_RX_ERGPIO0_40SPI6_D0UART2_TXDMCASP2_AFSX
0x1C09CWKUP_PADCONFIG_39 D9MCU_MDIO0_MDCWKUP_GPIO0_55
0x1C0A0WKUP_PADCONFIG_40 C13MCU_SPI0_CLKWKUP_GPIO0_56MCU_BOOTMODE00
0x1C0A0PADCONFIG_40 U12RGMII2_TX_CTLRMII2_TXD0GPIO0_41SPI6_D1UART4_RXDMCASP2_ACLKXGPMC0_A13
0x1C0A4WKUP_PADCONFIG_41 A20MCU_SPI0_D0WKUP_GPIO0_57MCU_BOOTMODE01
0x1C0A4PADCONFIG_41 W14UART8_RXDI2C4_SCLMDIO0_MDIOGPIO0_42TRC_DATA22UART8_RXDMCASP2_AFSRMCASP2_AXR4
0x1C0A8WKUP_PADCONFIG_42 B17MCU_SPI0_D1MCU_TIMER_IO0WKUP_GPIO0_58MCU_BOOTMODE02
0x1C0A8PADCONFIG_42 W19UART8_TXDSPI1_CS3I2C4_SDAMDIO0_MDCGPIO0_43TRC_DATA23UART8_TXDMCASP2_ACLKRMCASP2_AXR5
0x1C0ACWKUP_PADCONFIG_43 A19MCU_SPI0_CS0MCU_TIMER_IO1WKUP_GPIO0_59
0x1C0ACPADCONFIG_43 U13GPMC0_CLKUSB0_DRVVBUSRGMII4_RD3GPIO0_44SPI0_CS3UART9_RXD
0x1C0B0WKUP_PADCONFIG_44 B14WKUP_UART0_RXDWKUP_GPIO0_60
0x1C0B0PADCONFIG_44 T16UART0_RXDRGMII4_TXCGPIO0_47GPMC0_WAIT0
0x1C0B4PADCONFIG_45 T17UART0_TXDRGMII4_TD2GPIO0_48GPMC0_WEn
0x1C0B4WKUP_PADCONFIG_45 A14WKUP_UART0_TXDWKUP_GPIO0_61
0x1C0B8PADCONFIG_46 T18UART1_RXDMCAN17_TXTIMER_IO6RGMII4_TD3GPIO0_49GPMC0_OEn_REn
0x1C0B8WKUP_PADCONFIG_46 A16MCU_MCAN0_TXWKUP_GPIO0_62
0x1C0BCPADCONFIG_47 T20UART1_TXDMCAN17_RXTIMER_IO7RGMII4_TX_CTLGPIO0_50GPMC0_CSn0
0x1C0BCWKUP_PADCONFIG_47 A17MCU_MCAN0_RXWKUP_GPIO0_63
0x1C0C0PADCONFIG_48 W3SPI0_CS0UART0_CTSnGPIO0_51
0x1C0C0WKUP_PADCONFIG_48 B18MCU_SPI1_CLKMCU_SPI1_CLKWKUP_GPIO0_0MCU_BOOTMODE03
0x1C0C4PADCONFIG_49 U5SPI0_CS1CPTS0_TS_COMPUART0_RTSnGPIO0_52
0x1C0C4WKUP_PADCONFIG_49 B19MCU_SPI1_D0MCU_SPI1_D0WKUP_GPIO0_1MCU_BOOTMODE04
0x1C0C8PADCONFIG_50 Y1SPI0_CLKUART1_CTSnI2C2_SCLGPIO0_53
0x1C0C8WKUP_PADCONFIG_50 D14MCU_SPI1_D1MCU_SPI1_D1WKUP_GPIO0_2MCU_BOOTMODE05
0x1C0CCWKUP_PADCONFIG_51 B21MCU_SPI1_CS0MCU_SPI1_CS0WKUP_GPIO0_3
0x1C0CCPADCONFIG_51 V4SPI0_D0UART1_RTSnI2C2_SDAGPIO0_54
0x1C0D0WKUP_PADCONFIG_52 D13MCU_MCAN1_TXMCU_MCAN1_TXMCU_SPI0_CS3MCU_ADC_EXT_TRIGGER0WKUP_GPIO0_4
0x1C0D0PADCONFIG_52 T5SPI0_D1GPIO0_55
0x1C0D4PADCONFIG_53 V3I2C0_SCLGPIO0_56
0x1C0D4WKUP_PADCONFIG_53 B16MCU_MCAN1_RXMCU_MCAN1_RXMCU_SPI1_CS3MCU_ADC_EXT_TRIGGER1WKUP_GPIO0_5
0x1C0D8PADCONFIG_54 W2I2C0_SDAGPIO0_57
0x1C0D8WKUP_PADCONFIG_54 C14WKUP_UART0_CTSnWKUP_UART0_CTSnMCU_CPTS0_HW1TSPUSHMCU_I2C1_SCLWKUP_GPIO0_6
0x1C0DCPADCONFIG_55 U3ECAP0_IN_APWM_OUTSYNC0_OUTCPTS0_RFT_CLKI2C1_SCLCPTS0_HW1TSPUSHUART3_RXDSPI7_CS0GPIO0_58
0x1C0DCWKUP_PADCONFIG_55 C18WKUP_UART0_RTSnWKUP_UART0_RTSnMCU_CPTS0_HW2TSPUSHMCU_I2C1_SDAWKUP_GPIO0_7
0x1C0E0PADCONFIG_56 T3EXT_REFCLK1SYNC1_OUTI2C1_SDACPTS0_HW2TSPUSHUART3_TXDSPI7_CLKGPIO0_59
0x1C0E0WKUP_PADCONFIG_56 C21MCU_I2C1_SCLMCU_I2C1_SCLMCU_CPTS0_TS_SYNCMCU_I3C0_SCLMCU_TIMER_IO6WKUP_GPIO0_8
0x1C0E4PADCONFIG_57 V1TIMER_IO0ECAP1_IN_APWM_OUTSYSCLKOUT0UART3_CTSnSPI7_D0GPIO0_60MMC1_SDCD
0x1C0E4WKUP_PADCONFIG_57 C19MCU_I2C1_SDAMCU_I2C1_SDAMCU_CPTS0_TS_COMPMCU_I3C0_SDAMCU_TIMER_IO7WKUP_GPIO0_9
0x1C0E8PADCONFIG_58 W1TIMER_IO1ECAP2_IN_APWM_OUTOBSCLK0UART3_RTSnSPI7_D1GPIO0_61MMC1_SDWPPCIE1_CLKREQn
0x1C0E8WKUP_PADCONFIG_58 C20MCU_EXT_REFCLK0MCU_EXT_REFCLK0MCU_UART0_TXDMCU_ADC_EXT_TRIGGER0MCU_CPTS0_RFT_CLKMCU_SYSCLKOUT0WKUP_GPIO0_10
0x1C0ECWKUP_PADCONFIG_59 C16MCU_OBSCLK0MCU_OBSCLK0MCU_UART0_RXDMCU_ADC_EXT_TRIGGER1MCU_TIMER_IO1MCU_I3C0_SDAPULLENMCU_CLKOUT0WKUP_GPIO0_11
0x1C0ECPADCONFIG_59 N19MMC1_DAT3UART7_RXDPCIE1_CLKREQnTIMER_IO0GPIO0_62SPI1_CS0UART0_CTSnI2C3_SCLUART5_RXD
0x1C0F0WKUP_PADCONFIG_60 D19MCU_UART0_TXDMCU_SPI0_CS1WKUP_GPIO0_12MCU_BOOTMODE08
0x1C0F0PADCONFIG_60 N20MMC1_DAT2UART7_TXDTIMER_IO1GPIO0_63SPI1_CS1CPTS0_TS_SYNCI2C3_SDAUART5_TXD
0x1C0F4PADCONFIG_61 N21MMC1_DAT1UART7_CTSnECAP0_IN_APWM_OUTTIMER_IO2UART4_RXDGPIO0_64SPI1_CS2UART5_CTSnI2C4_SDAUART2_RXD
0x1C0F4WKUP_PADCONFIG_61 D20MCU_UART0_RXDMCU_SPI1_CS1WKUP_GPIO0_13MCU_BOOTMODE09
0x1C0F8PADCONFIG_62 M19MMC1_DAT0UART7_RTSnECAP1_IN_APWM_OUTTIMER_IO3UART4_TXDGPIO0_65SPI1_D0UART5_RTSnI2C4_SCLUART2_TXD
0x1C0F8WKUP_PADCONFIG_62 E20MCU_UART0_CTSnMCU_SPI0_CS2MCU_TIMER_IO8WKUP_GPIO0_14MCU_BOOTMODE06
0x1C0FCWKUP_PADCONFIG_63 E21MCU_UART0_RTSnMCU_SPI1_CS2MCU_TIMER_IO9WKUP_GPIO0_15MCU_BOOTMODE07
0x1C100PADCONFIG_64 P21MMC1_CLKUART8_RXDTIMER_IO4UART4_CTSnGPIO0_66SPI1_CLKUART0_RTSnI2C6_SDA
0x1C100WKUP_PADCONFIG_64 F20WKUP_I2C0_SCLWKUP_GPIO0_64
0x1C104PADCONFIG_65 M20MMC1_CMDUART8_TXDTIMER_IO5UART4_RTSnGPIO0_67SPI1_D1I2C6_SCL
0x1C104WKUP_PADCONFIG_65 H21WKUP_I2C0_SDAWKUP_GPIO0_65
0x1C108WKUP_PADCONFIG_66 G21MCU_I2C0_SCLWKUP_GPIO0_66
0x1C108PADCONFIG_66 U2RESETSTATz
0x1C10CWKUP_PADCONFIG_67 G20MCU_I2C0_SDAWKUP_GPIO0_67
0x1C110WKUP_PADCONFIG_68 C15PMIC_POWER_EN1MCU_I3C0_SDAPULLENWKUP_GPIO0_68
0x1C110PADCONFIG_68 V2SOC_SAFETY_ERRORn
0x1C114WKUP_PADCONFIG_69 G18MCU_SAFETY_ERRORn
0x1C118WKUP_PADCONFIG_70 A18MCU_RESETz
0x1C11CPADCONFIG_71 U4TMS
0x1C11CWKUP_PADCONFIG_71 B13MCU_RESETSTATzWKUP_GPIO0_79
0x1C120WKUP_PADCONFIG_72 D21MCU_TIMER_IO6WKUP_GPIO0_77BOOTMODE04
0x1C120PADCONFIG_72 T4USB0_DRVVBUSGPIO0_68
0x1C124WKUP_PADCONFIG_73 B15TCK
0x1C124PADCONFIG_73 T19PMIC_WAKE0nRGMII4_TD1GPIO0_1
0x1C128WKUP_PADCONFIG_74 B20TRSTn
0x1C12CWKUP_PADCONFIG_75 A13EMU0
0x1C130WKUP_PADCONFIG_76 D12EMU1
0x1C134WKUP_PADCONFIG_77 H17MCU_ADC0_AIN0
0x1C138WKUP_PADCONFIG_78 K18MCU_ADC0_AIN1
0x1C13CWKUP_PADCONFIG_79 M17MCU_ADC0_AIN2
0x1C140WKUP_PADCONFIG_80 L18MCU_ADC0_AIN3
0x1C144WKUP_PADCONFIG_81 J18MCU_ADC0_AIN4
0x1C148WKUP_PADCONFIG_82 J17MCU_ADC0_AIN5
0x1C14CWKUP_PADCONFIG_83 K17MCU_ADC0_AIN6
0x1C150WKUP_PADCONFIG_84 L17MCU_ADC0_AIN7
0x1C164PADCONFIG_89 V15MCAN16_TXRMII_REF_CLKRGMII4_RX_CTLGPIO0_45UART7_TXDGPMC0_A14
0x1C168PADCONFIG_90 U21MCAN16_RXCLKOUTRGMII4_TD0GPIO0_46UART7_RXDGPMC0_CSn1AUDIO_EXT_REFCLK1
0x1C174WKUP_PADCONFIG_93 A15RESET_REQz
0x1C178WKUP_PADCONFIG_94 H20PORz
0x1C17CWKUP_PADCONFIG_95 E19MCU_TIMER_IO7WKUP_GPIO0_78BOOTMODE05
0x1C180WKUP_PADCONFIG_96 D18WKUP_GPIO0_80BOOTMODE06
0x1C184WKUP_PADCONFIG_97 C17WKUP_LF_CLKINWKUP_GPIO0_81BOOTMODE07
0x1C188WKUP_PADCONFIG_98 F19TDI
0x1C18CWKUP_PADCONFIG_99 F21TDO
0x1C190WKUP_PADCONFIG_100 E18PMIC_WAKE1nMCU_EXT_REFCLK0MCU_CPTS0_RFT_CLKWKUP_GPIO0_84