ZHCSNQ7C December 2020 – November 2022 DP83TG720R-Q1
PRODUCTION DATA
Table 8-22 lists the memory-mapped registers for the DP83TG720 registers. All register offset addresses not listed in Table 8-22 should be considered as reserved locations and the register contents should not be modified.
BMCR is shown in Figure 8-18 and described in Table 8-23.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mii_reset | loopback | RESERVED | RESERVED | power_down | isolate | RESERVED | RESERVED |
| R/WMC-0h | R/W-0h | R-0h | R-0h | R/W-0h | R/W-0h | R-0h | R-1h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | speed_sel_msb | RESERVED | RESERVED | ||||
| R-0h | R-1h | R-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | mii_reset | R/WMC | 0h | 1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default 0b = No reset |
| 14 | loopback | R/W | 0h | 1b = MII loopback 0b = No MII loopback |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | power_down | R/W | 0h | 1b = Power down via register or pin 0b = Normal mode |
| 10 | isolate | R/W | 0h | 1b = MAC isolate mode (No output to MAC from the PHY) 0b = Normal Mode |
| 9 | RESERVED | R | 0h | Reserved |
| 8 | RESERVED | R | 1h | Reserved |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | speed_sel_msb | R | 1h | 0b= Reserved 1b= 1000 Mb/s |
| 5 | RESERVED | R | 0h | Reserved |
| 4-0 | RESERVED | R | 0h | Reserved |
BMSR is shown in Figure 8-19 and described in Table 8-24.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | extended_status |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-1h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| unidirectional_ability | preamble_supression | aneg_complete | remote_fault | aneg_ability | link_status | jabber_detect | extended_capability |
| R-0h | R-1h | R-0h | R/W0C-0h | R-0h | R/W0S-0h | R/W0C-0h | R-1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | RESERVED | R | 0h | Reserved |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | RESERVED | R | 0h | Reserved |
| 10 | RESERVED | R | 0h | Reserved |
| 9 | RESERVED | R | 0h | Reserved |
| 8 | extended_status | R | 1h | 1b = Extended status information in Register 15 0b = No extended status information in Register 15 |
| 7 | unidirectional_ability | R | 0h | Reserved |
| 6 | preamble_supression | R | 1h | 1b = PHY will accept management frames with preamble suppressed. 0b = PHY will not accept management frames with preamble suppressed |
| 5 | aneg_complete | R | 0h | Reserved |
| 4 | remote_fault | R/W0C | 0h | Reserved |
| 3 | aneg_ability | R | 0h | Reserved |
| 2 | link_status | R/W0S | 0h | 1b = link is up 0b = link down |
| 1 | jabber_detect | R/W0C | 0h | Reserved |
| 0 | extended_capability | R | 1h | 1b = extended register capabilities 0b = basic register set capabilities only |
PHYID1 is shown in Figure 8-20 and described in Table 8-25.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| oui_21_16 | |||||||
| R-2000h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| oui_21_16 | |||||||
| R-2000h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | oui_21_16 | R | 2000h | Unique identifier for the part |
PHYID2 is shown in Figure 8-21 and described in Table 8-26.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| oui_5_0 | model_number | ||||||
| R-28h | R-28h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| model_number | rev_number | ||||||
| R-28h | R-4h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | oui_5_0 | R | 28h | Unique identifier for the part |
| 9-4 | model_number | R | 28h | Unique identifier for the part |
| 3-0 | rev_number | R | 4h | Unique identifier for the part |
REGCR is shown in Figure 8-22 and described in Table 8-27.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Extended Register Command | RESERVED | ||||||
| R/W-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DEVAD | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | Extended Register Command | R/W | 0h | 00b = Address 01b = Data, no post increment 10b = Data, post increment on read and write 11b = Data, post increment on write only |
| 13-5 | RESERVED | R/W | 0h | Reserved |
| 4-0 | DEVAD | R/W | 0h | RESERVED |
ADDAR is shown in Figure 8-23 and described in Table 8-28.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Address/Data | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Address/Data | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | Address/Data | R/W | 0h |
MII_REG_10 is shown in Figure 8-24 and described in Table 8-29.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | signal_detect | descr_lock_bit | RESERVED | ||||
| R-0h | R/W0S-0h | R/W0S-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mii_int_bit | RESERVED | mii_loopback | duplex_mode_env | RESERVED | link_status_bit | ||
| 0h | R-0h | R-0h | R-1h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | signal_detect | R/W0S | 0h | 1b = Channel ok is set 0b = Channel ok had been reset |
| 9 | descr_lock_bit | R/W0S | 0h | 1b = Descrambler is locked 0b = Descrmabler had been locked |
| 8 | RESERVED | R | 0h | Reserved |
| 7 | mii_int_bit | 0h | 1b = Interrupt pin had been set 0b = Interrupts pin not set | |
| 6-4 | RESERVED | R | 0h | Reserved |
| 3 | mii_loopback | R | 0h | 1b = MII loopback 0b = No MII loopback |
| 2 | duplex_mode_env | R | 1h | 1b = Full duplex 0b = Half duplex |
| 1 | RESERVED | R | 0h | Reserved |
| 0 | link_status_bit | R | 0h | 1b = link is up 0b = link had been down |
MII_REG_11 is shown in Figure 8-25 and described in Table 8-30.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
| R/W-0h | R/W-0h | R/W-0h | R/WSC-0h | R/W-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | int_polarity | force_interrupt | int_en | RESERVED | |
| R-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-1h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0h | Reserved |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13-12 | RESERVED | R/W | 0h | Reserved |
| 11 | RESERVED | R/WSC | 0h | Reserved |
| 10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R/W | 0h | Reserved |
| 8 | RESERVED | R/W | 0h | Reserved |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | RESERVED | R/W | 0h | Reserved |
| 5-4 | RESERVED | R/W | 0h | Reserved |
| 3 | int_polarity | R/W | 1h | 1b = Active low 0b = Active high |
| 2 | force_interrupt | R/W | 0h | 1b = Force interrupt pin 0b = Do not force interrupt pin |
| 1 | int_en | R/W | 1h | 1b = Enable interrupts 0b = Disable interrupts |
| 0 | RESERVED | R/W | 1h | Reserved |
MII_REG_12 is shown in Figure 8-26 and described in Table 8-31.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| link_qual_int | energy_det_int | link_int | RESERVED | esd_int | ms_train_done_int | RESERVED | RESERVED |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| link_qual_int_en | energy_det_int_en | link_int_en | unused_int_3 | esd_int_en | ms_train_done_int_en | unused_int_2 | unused_int_1 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | link_qual_int | R | 0h | Link quality bad interrupt status |
| 14 | energy_det_int | R | 0h | Energy det change interrupt status |
| 13 | link_int | R | 0h | Link status change interrupt status |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | esd_int | R | 0h | ESD fault detected interrupt status |
| 10 | ms_train_done_int | R | 0h | Training done interrupt status |
| 9 | RESERVED | R | 0h | Reserved |
| 8 | RESERVED | R | 0h | Reserved |
| 7 | link_qual_int_en | R/W | 0h | Link quality bad interrupt enable |
| 6 | energy_det_int_en | R/W | 0h | Energy det change interrupt enable |
| 5 | link_int_en | R/W | 0h | Link status change interrupt enable |
| 4 | unused_int_3 | R/W | 0h | Reserved |
| 3 | esd_int_en | R/W | 0h | ESD fault detected interrupt enable |
| 2 | ms_train_done_int_en | R/W | 0h | Training done interrupt enable |
| 1 | unused_int_2 | R/W | 0h | Reserved |
| 0 | unused_int_1 | R/W | 0h | Reserved |
MII_REG_13 is shown in Figure 8-27 and described in Table 8-32.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| under_volt_int | over_volt_int | RESERVED | RESERVED | over_temp_int | sleep_int | pol_change_int | not_one_hot_int |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| under_volt_int_en | over_volt_int_en | unused_int_6 | unused_int_5 | over_temp_int_en | sleep_int_en | pol_change_int_en | not_one_hot_int_en |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | under_volt_int | R | 0h | Under volt interrupt status |
| 14 | over_volt_int | R | 0h | Over volt interrupt status |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | over_temp_int | R | 0h | Over temp interrupt status |
| 10 | sleep_int | R | 0h | Sleep mode change interrupt status |
| 9 | pol_change_int | R | 0h | Data polarity change interrupt status |
| 8 | not_one_hot_int | R | 0h | Not one hot interrupt status |
| 7 | under_volt_int_en | R/W | 0h | Under volt interrupt enable |
| 6 | over_volt_int_en | R/W | 0h | Over volt interrupt enable |
| 5 | unused_int_6 | R/W | 0h | Reserved |
| 4 | unused_int_5 | R/W | 0h | Reserved |
| 3 | over_temp_int_en | R/W | 0h | Over temp interrupt enable |
| 2 | sleep_int_en | R/W | 0h | Sleep mode change interrupt enable |
| 1 | pol_change_int_en | R/W | 0h | Data Polarity change interrupt enable |
| 0 | not_one_hot_int_en | R/W | 0h | Not one hot interrupt enable |
MII_REG_16 is shown in Figure 8-28 and described in Table 8-33.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | prbs_sync_loss | RESERVED | core_pwr_mode | ||||
| R-0h | R/W0C-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_dig_pcs_loopback | loopback_mode | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | prbs_sync_loss | R/W0C | 0h | 1b = Prbs lock had been lost 0b = Prbs lock never lost |
| 9 | RESERVED | R | 0h | Reserved |
| 8 | core_pwr_mode | R | 0h | 1b = Core is is normal power mode 0b = Core is in power down or sleep mode |
| 7 | cfg_dig_pcs_loopback | R/W | 0h | PCS digital loopback |
| 6-0 | loopback_mode | R/W | 0h | 000001b = PCS loop 000010b = RS loop 000100b = Digital loop 001000B = Analog loop 010000b = Reverse loop |
MII_REG_18 is shown in Figure 8-29 and described in Table 8-34.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ack_received_int | tx_valid_clr_int | RESERVED | RESERVED | por_done_int | no_frame_int | wake_req_int | lps_int |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ack_received_int_en | tx_valid_clr_int_en | RESERVED | RESERVED | por_done_int_en | no_frame_int_en | wake_req_int_en | lps_int_en |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ack_received_int | R | 0h | Ack received interrupt status (OAM) |
| 14 | tx_valid_clr_int | R | 0h | mr_tx_valid clear interrupt status (OAM) |
| 13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | por_done_int | R | 0h | POR done interrupt status |
| 10 | no_frame_int | R | 0h | No frame detect interrupt status |
| 9 | wake_req_int | R | 0h | Wake request interrupt status |
| 8 | lps_int | R | 0h | LPS interrupt status |
| 7 | ack_received_int_en | R/W | 0h | Ack received interrupt enable (OAM) |
| 6 | tx_valid_clr_int_en | R/W | 0h | mr_tx_valid clear interrupt enable (OAM) |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | RESERVED | R/W | 0h | Reserved |
| 3 | por_done_int_en | R/W | 1h | POR done interrupt enable |
| 2 | no_frame_int_en | R/W | 0h | No frame detect interrupt enable |
| 1 | wake_req_int_en | R/W | 0h | Wake request interrupt enable |
| 0 | lps_int_en | R/W | 0h | LPS interrupt enable |
MII_REG_19 is shown in Figure 8-30 and described in Table 8-35.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | |||||
| R-0h | R-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOR_PHYADDR | ||||||
| R-0h | R-X | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | RESERVED | R | 0h | Reserved |
| 9-5 | RESERVED | R | 0h | Reserved |
| 4-0 | SOR_PHYADDR | R | X | PHY ADDRESS latched from strap |
MII_REG_1E is shown in Figure 8-31 and described in Table 8-36.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tdr_start | cfg_tdr_auto_run | RESERVED | |||||
| R/WMC-0h | R/W-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | tdr_done | tdr_fail | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | tdr_start | R/WMC | 0h | 1b = TDR start 0b = No TDR |
| 14 | cfg_tdr_auto_run | R/W | 0h | 1b = TDR start automatically on link down 0b = TDR start manually |
| 13-2 | RESERVED | R | 0h | Reserved |
| 1 | tdr_done | R | 0h | TDR done status |
| 0 | tdr_fail | R | 0h | TDR fail status |
MII_REG_1F is shown in Figure 8-32 and described in Table 8-37.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| sw_global_reset | digital_reset | RESERVED | RESERVED | ||||
| R/WMC-0h | R/WMC-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | ||||
| R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | sw_global_reset | R/WMC | 0h | Hardware reset - Reset digital + register file |
| 14 | digital_reset | R/WMC | 0h | Soft reset - Reset only digital core |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12-8 | RESERVED | R/W | 0h | Reserved |
| 7 | RESERVED | R/W | 0h | Reserved |
| 6 | RESERVED | R/W | 0h | Reserved |
| 5 | RESERVED | R | 0h | Reserved |
| 4-0 | RESERVED | R/W | 0h | Reserved |
LSR is shown in Figure 8-33 and described in Table 8-38.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| link_up | link_down | phy_ctrl_send_data | link_status | RESERVED | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | descr_sync | loc_rcvr_status | rem_rcvr_status |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | link_up | R | 0h | Link up defined by CnS |
| 14 | link_down | R | 0h | Link down as defined by CnS |
| 13 | phy_ctrl_send_data | R | 0h | Phy control in send data status |
| 12 | link_status | R | 0h | Link status |
| 11-8 | RESERVED | R | 0h | Reserved |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | RESERVED | R | 0h | Reserved |
| 5 | RESERVED | R | 0h | Reserved |
| 4 | RESERVED | R | 0h | Reserved |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | descr_sync | R | 0h | Descrambler lock status |
| 1 | loc_rcvr_status | R | 0h | Local receiver status |
| 0 | rem_rcvr_status | R | 0h | Remote receiver status |
LPS_CFG2 is shown in Figure 8-34 and described in Table 8-39.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ed_en | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sleep_en | cfg_auto_mode_en_strap | cfg_lps_mon_en_strap | cfg_lps_sleep_auto | cfg_lps_slp_confirm | cfg_lps_auto_pwrdn | cfg_lps_sleep_en | cfg_lps_sm_en |
| R/W-0h | R/WMC,1-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | ed_en | R/W | 0h | 1b = Enable energy detection on MDI 0b = Disable energy detection on MDI |
| 7 | sleep_en | R/W | 0h | 1b = Allow PHY to enter sleep 0b = Do not allow PHY to enter sleep |
| 6 | cfg_auto_mode_en_strap | R/WMC,1 | 0h | LPS autonomous mode enable 1b = PHY enters normal mode on power up 0b = PHY enters standby mode on power up |
| 5 | cfg_lps_mon_en_strap | R/W | 0h | |
| 4 | cfg_lps_sleep_auto | R/W | 0h | Reserved |
| 3 | cfg_lps_slp_confirm | R/W | 0h | Reserved |
| 2 | cfg_lps_auto_pwrdn | R/W | 0h | Reserved |
| 1 | cfg_lps_sleep_en | R/W | 0h | Reserved |
| 0 | cfg_lps_sm_en | R/W | 0h | Reserved |
LPS_CFG3 is shown in Figure 8-35 and described in Table 8-40.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_lps_pwr_mode_7 | cfg_lps_pwr_mode_6 | cfg_lps_pwr_mode_5 | cfg_lps_pwr_mode_4 | cfg_lps_pwr_mode_3 | cfg_lps_pwr_mode_2 | cfg_lps_pwr_mode_1 | cfg_lps_pwr_mode_0 |
| R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h | R/WMC,0-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7 | cfg_lps_pwr_mode_7 | R/WMC,0 | 0h | Reserved |
| 6 | cfg_lps_pwr_mode_6 | R/WMC,0 | 0h | Reserved |
| 5 | cfg_lps_pwr_mode_5 | R/WMC,0 | 0h | Reserved |
| 4 | cfg_lps_pwr_mode_4 | R/WMC,0 | 0h | Set to enter standby mode |
| 3 | cfg_lps_pwr_mode_3 | R/WMC,0 | 0h | Reserved |
| 2 | cfg_lps_pwr_mode_2 | R/WMC,0 | 0h | Reserved |
| 1 | cfg_lps_pwr_mode_1 | R/WMC,0 | 0h | Reserved |
| 0 | cfg_lps_pwr_mode_0 | R/WMC,0 | 0h | Set to enter normal mode |
TDR_STATUS0 is shown in Figure 8-36 and described in Table 8-41.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| peak1_loc | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| peak0_loc | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | peak1_loc | R | 0h | Peak 1 location in tap index |
| 7-0 | peak0_loc | R | 0h | Peak 0 location in tap index |
TDR_STATUS1 is shown in Figure 8-37 and described in Table 8-42.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| peak3_loc | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| peak2_loc | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | peak3_loc | R | 0h | Peak 3 location in tap index |
| 7-0 | peak2_loc | R | 0h | Peak 2 location in tap index |
TDR_STATUS2 is shown in Figure 8-38 and described in Table 8-43.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| peak0_amp | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| peak4_loc | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | peak0_amp | R | 0h | Peak 0 amplitude in echo coeff |
| 7-0 | peak4_loc | R | 0h | Peak 4 location in tap index |
TDR_STATUS5 is shown in Figure 8-39 and described in Table 8-44.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | peak4_sign | peak3_sign | peak2_sign | peak1_sign | peak0_sign | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-5 | RESERVED | R | 0h | Reserved |
| 4 | peak4_sign | R | 0h | Peak 4 sign |
| 3 | peak3_sign | R | 0h | Peak 3 sign |
| 2 | peak2_sign | R | 0h | Peak 2 sign |
| 1 | peak1_sign | R | 0h | Peak 1 sign |
| 0 | peak0_sign | R | 0h | Peak 0 sign |
TDR_TC12 is shown in Figure 8-40 and described in Table 8-45.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | fault_loc | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tdr_state | RESERVED | tdr_activation | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-8 | fault_loc | R | 0h | See TC12 |
| 7-4 | tdr_state | R | 0h | See TC12 |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1-0 | tdr_activation | R | 0h | See TC12 |
A2D_REG_05 is shown in Figure 8-41 and described in Table 8-46.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ld_bias_1p0v_sl | RESERVED | ||||||
| R/W-19h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | ld_bias_1p0v_sl | R/W | 19h | Bits to control the DAC current of LD and hence the swing. 001010b = 400 mV 001011b = 440 mV 001100b = 480 mV 001101b = 520 mV 001110b = 560 mV 001111b = 600 mV 010000b = 640 mV 010001b = 680 mV 010010b = 720 mV 010011b = 760 mV 010100b = 800 mV 010101b = 840 mV 010110b = 880 mV 010111b = 920 mV 011000b = 960 mV 011001b = 1000 mV 011010b = 1040 mV 011011b = 1080 mV 011100b = 1120 mV 011101b = 1160 mV 011110b = 1200 mV |
| 9-0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_30 is shown in Figure 8-42 and described in Table 8-47.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | spare_in_2_fromdig_sl_force_en | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | spare_in_2_fromdig_sl_force_en | R/W | 0h | Force control enable for Reg0x042F |
| 7 | RESERVED | R/W | 0h | Reserved |
| 6 | RESERVED | R/W | 0h | Reserved |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | RESERVED | R/W | 0h | Reserved |
| 3-0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_31 is shown in Figure 8-43 and described in Table 8-48.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0h | Reserved |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12 | RESERVED | R/W | 0h | Reserved |
| 11 | RESERVED | R/W | 0h | Reserved |
| 10-7 | RESERVED | R/W | 0h | Reserved |
| 6-3 | RESERVED | R/W | 0h | Reserved |
| 2 | RESERVED | R/W | 0h | Reserved |
| 1 | RESERVED | R/W | 0h | Reserved |
| 0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_40 is shown in Figure 8-44 and described in Table 8-49.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SGMII_TESTMODE | RESERVED | SGMII_SOP_SON_SLEW_CTRL | RESERVED | RESERVED | ||
| R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | |||||
| R/W-0h | R/W-1h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0h | Reserved |
| 14-13 | SGMII_TESTMODE | R/W | 3h | 00b = 1000mV Sgmii output swing 01b = 1260mV Sgmii output swing 10b = 900mV Sgmii output swing 11b = 720mV Sgmii output swing |
| 12 | RESERVED | R/W | 0h | Reserved |
| 11 | SGMII_SOP_SON_SLEW_CTRL | R/W | 0h | 0b =Default output rise/fall time 1b = Slow output rise/fall time |
| 10 | RESERVED | R/W | 0h | Reserved |
| 9-8 | RESERVED | R/W | 0h | Reserved |
| 7 | RESERVED | R/W | 0h | Reserved |
| 6-1 | RESERVED | R/W | 1h | Reserved |
| 0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_41 is shown in Figure 8-45 and described in Table 8-50.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SGMII_IO_LOOPBACK_EN | RESERVED | |||||
| R/W-Ch | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R/W | 0h | Reserved |
| 10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R/W | 0h | Reserved |
| 8 | RESERVED | R/W | 0h | Reserved |
| 7-2 | RESERVED | R/W | Ch | Reserved |
| 1 | SGMII_IO_LOOPBACK_EN | R/W | 0h | 1b = Connects RX and TX signals internally to provide internal loopback option without external components. |
| 0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_43 is shown in Figure 8-46 and described in Table 8-51.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SGMII_CDR_TESTMODE_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SGMII_CDR_TESTMODE_1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | SGMII_CDR_TESTMODE_1 | R/W | 0h | SGMII RX CDR test mode |
A2D_REG_44 is shown in Figure 8-47 and described in Table 8-52.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | SGMII_DIG_LOOPBACK_EN | RESERVED | RESERVED | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0h | Reserved |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12 | RESERVED | R/W | 0h | Reserved |
| 11 | RESERVED | R/W | 0h | Reserved |
| 10 | RESERVED | R/W | 0h | Reserved |
| 9 | RESERVED | R/W | 0h | Reserved |
| 8 | RESERVED | R/W | 0h | Reserved |
| 7 | RESERVED | R/W | 0h | Reserved |
| 6 | RESERVED | R/W | 0h | Reserved |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | SGMII_DIG_LOOPBACK_EN | R/W | 0h | 1b = Loops back TX data to RX before the IO |
| 3-1 | RESERVED | R/W | 0h | Reserved |
| 0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_46 is shown in Figure 8-48 and described in Table 8-53.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | sgmii_calib_watchdog_dis | sgmii_calib_watchdog_val | sgmii_calib_avg | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sgmii_calib_avg | sgmii_do_calib | SGMII_CDR_LOCK_SL | SGMII_MODE_force_en | SGMII_INPUT_TERM_EN_force_en | SGMII_OUTPUT_EN_force_en | SGMII_COMP_OFFSET_TUNE_force_en | SGMII_DATA_SYNC_SL |
| R/W-0h | R/WSC-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11 | sgmii_calib_watchdog_dis | R/W | 0h | By default, SGMII calibration process has a watchdog timer. If calibration is not ended till timer expires, then it is dsabled and default value is taken. If this bit is set, then the calibration watchdog timer is disabled. |
| 10-9 | sgmii_calib_watchdog_val | R/W | 0h | Watchdog timer configuration for SGMII calibration sequence: 00 - If not ended, calibration stops after 32us 01 - If not ended, calibration stops after 48us 10 - If not ended, calibration stops after 64us 11 - If not ended, calibration stops after 128us |
| 8-7 | sgmii_calib_avg | R/W | 0h | Number of repetitions of COMP_OFFSET_TUNE calibration (the repetitions are for averaging): 00 - a single repetition 01 - 2 repetitions 10 - 4 repetitions 11 - 8 repetitions |
| 6 | sgmii_do_calib | R/WSC | 0h | SGMII start calibration command (mainly for debug) Please notice: This register is WSC (write-self-clear) and not read-only! |
| 5 | SGMII_CDR_LOCK_SL | R | 0h | Indicates Sgmiis CDR lock status |
| 4 | SGMII_MODE_force_en | R/W | 0h | |
| 3 | SGMII_INPUT_TERM_EN_force_en | R/W | 0h | |
| 2 | SGMII_OUTPUT_EN_force_en | R/W | 0h | |
| 1 | SGMII_COMP_OFFSET_TUNE_force_en | R/W | 0h | |
| 0 | SGMII_DATA_SYNC_SL | R | 0h |
A2D_REG_47 is shown in Figure 8-49 and described in Table 8-54.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | spare_in_2_fromdig_sl_2 | spare_in_2_fromdig_sl_1 | spare_in_2_fromdig_sl_0 | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R/W | 0h | Reserved |
| 3 | RESERVED | R/W | 0h | Reserved |
| 2 | spare_in_2_fromdig_sl_2 | R/W | 0h | energy lost indication force control value |
| 1 | spare_in_2_fromdig_sl_1 | R/W | 0h | energy lost detector enable force control value |
| 0 | spare_in_2_fromdig_sl_0 | R/W | 0h | [0] - sleep enable force control value Force control enable is controlled by reg0x041E[8] |
A2D_REG_48 is shown in Figure 8-50 and described in Table 8-55.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | DLL_EN | DLL_TX_DELAY_CTRL_SL | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-9h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLL_RX_DELAY_CTRL_SL | RESERVED | ||||||
| R/W-6h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12 | DLL_EN | R/W | 0h | |
| 11-8 | DLL_TX_DELAY_CTRL_SL | R/W | 9h | Refer to electrical specification for delay vs code information. |
| 7-4 | DLL_RX_DELAY_CTRL_SL | R/W | 6h | Refer to electrical specification for delay vs code information. |
| 3-0 | RESERVED | R/W | 0h | Reserved |
A2D_REG_66 is shown in Figure 8-51 and described in Table 8-56.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | esd_event_count | RESERVED | |||||
| R/W-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0h | Reserved |
| 14-9 | esd_event_count | R | 0h | Number gives the number of esd events on the copper channel |
| 8 | RESERVED | R/W | 0h | Reserved |
| 7-5 | RESERVED | R/W | 0h | Reserved |
| 4 | RESERVED | R/W | 0h | Reserved |
| 3-0 | RESERVED | R/W | 0h | Reserved |
LEDS_CFG_1 is shown in Figure 8-52 and described in Table 8-57.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | leds_bypass_stretching | leds_blink_rate | led_2_option | ||||
| R-0h | R/W-0h | R/W-2h | R/W-6h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| led_1_option | led_0_option | ||||||
| R/W-1h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | |
| 14 | leds_bypass_stretching | R/W | 0h | LED Signal Stretch |
| 13-12 | leds_blink_rate | R/W | 2h | Blink Rate for the LED - 00b = 20Hz (50mSec) 01b = 10Hz (100mSec) 10b = 5Hz (200mSec) 11b = 2Hz (500mSec) |
| 11-8 | led_2_option | R/W | 6h | 0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option |
| 7-4 | led_1_option | R/W | 1h | 0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error (latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option |
| 3-0 | led_0_option | R/W | 0h | 0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error (latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option |
LEDS_CFG_2 is shown in Figure 8-53 and described in Table 8-58.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | XXXX | led_2_drv_en | ||||
| R-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| led_2_drv_val | led_2_polarity | led_1_drv_en | led_1_drv_val | led_1_polarity | led_0_drv_en | led_0_drv_val | led_0_polarity |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-10 | RESERVED | R | 0h | Reserved |
| 11-9 | cfg_ieee_compl_sel | R/W | 0h | Observe IEEE Compliance signals in LED_0_GPIO_0, when LED_0_GPIO_CTRL= 'h5 as follows - 000b = loc_rcvr_status 001b = rem_rcvr_status 010b = loc_snr_margin 011b = rem_phy_ready 100b = pma_watchdog_status 101b = link_sync_link_control |
| 8 | led_2_drv_en | R/W | 0h | LED_2 Drive Enable, When set, drives the value as per LED_2_DRV_VAL |
| 7 | led_2_drv_val | R/W | 0h | LED_2 Drive Value, when LED_2_DRV_EN is set |
| 6 | led_2_polarity | R/W | 0h | LED_2 polarity |
| 5 | led_1_drv_en | R/W | 0h | LED_1 Drive Enable, When set, drives the value as per LED_1_DRV_VAL |
| 4 | led_1_drv_val | R/W | 0h | LED_1 Drive Value, when LED_1_DRV_EN is set |
| 3 | led_1_polarity | R/W | 0h | LED_1 polarity |
| 2 | led_0_drv_en | R/W | 0h | LED_0 Drive Enable, When set, drives the value as per LED_0_DRV_VAL |
| 1 | led_0_drv_val | R/W | 0h | LED_0 Drive Value, when LED_0_DRV_EN is set |
| 0 | led_0_polarity | R/W | 0h | LED_0 polarity |
IO_MUX_CFG_1 is shown in Figure 8-54 and described in Table 8-59.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | led_1_gpio_ctrl | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | led_0_gpio_ctrl | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-11 | RESERVED | R/W | 0h | Reserved |
| 10-8 | led_1_gpio_ctrl | R/W | 0h | Controls the output of LED_1 IO - 000b = LED_1 (default: link OK + blink on TX/RX activity) 001b = Reserved 010b = RGMII data match indication 011b = Under-Voltage indication 100b = Interrupt 101b = IEEE compliance signals 110b = constant 0 111b = constant 1 |
| 7-6 | RESERVED | R | 0h | Reserved |
| 5-3 | RESERVED | R/W | 0h | Reserved |
| 2-0 | led_0_gpio_ctrl | R/W | 0h | Controls the output of LED_0 IO: 000b = LED_0 (default: LINK) 001b = Reserved 010b = RGMII data match indication 011b = Under-Voltage indication 100b = Interrupt 101b = IEEE compliance signals (see 0x451[11:9]) 110b = constant 0 111b = constant 1 |
IO_MUX_CFG_2 is shown in Figure 8-55 and described in Table 8-60.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | clk_o_clk_source | clk_o_gpio_ctrl | |||||
| R-0h | R/W-0h | R/W-1h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-6 | RESERVED | R | 0h | Reserved |
| 5-3 | clk_o_clk_source | R/W | 0h | Clock Observable in CLK_O pin - 000b = xi_osc_25m_1p0v_dl (25MHz crystal output - from analog) 001b = Reserved 010b = Reserved 011b = 125MHz clock 100b = 125MHz clock 101b = Reserved 110b = Reserved 111b = Reserved |
| 2-0 | clk_o_gpio_ctrl | R/W | 1h | Controls the output of CLK_O IO - 000b = LED_2 (default: TX/RX activity with stretch option(LED_2_OPTION=0x6) 001b = Clock out (see 0x453[5:3]) 010b = RGMII data match indication 011b = Under-Voltage indication 100b = constant 0 101b = constant 0 110b = constant 0 111b = constant 1 |
IO_CONTROL_1 is shown in Figure 8-56 and described in Table 8-61.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| io_control_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| io_control_1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | io_control_1 | R/W | 0h | IO_CONTROL_1 : IO reflects the value written on this register when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=0 If 0 is written, IO will be forced to ouput LOW. If 1 is written, IO will be forced to ouput HIGH. The following is the bit position for pads. 0=LED_0_GPIO_0; 1=LED_1_GPIO_1; 2=CLKOUT_GPIO_2; 3=INT_N; 4=RESERVED; 5=RESERVED; 6=INH; 7=TX_CLK; 8=TX_CTRL; 9=TX_D0; 10=TX_D1; 11=TX_D2; 12=TX_D3; 13=RX_CLK; 14=RX_CTRL; 15=RX_D0; |
IO_CONTROL_2 is shown in Figure 8-57 and described in Table 8-62.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_other_impedance | pupd_value | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pupd_value | pupd_force_cntl | io_oe_n_value | io_oe_n_force_ctrl | io_control_2 | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-9 | cfg_other_impedance | R/W | 0h | Slew Rate Control for CLKOUT - 00000b = Default rise/fall time 00001b = Slower rise/fall time 00010b = Faster rise/fall time |
| 8-7 | pupd_value | R/W | 0h | IO Test mode - pullup/pull down : 00b = No pull (HiZ) 01b = PullUP 10b = PullDown 11b = PullUp/PullDown (Both Enabled) |
| 6 | pupd_force_cntl | R/W | 0h | IO Test mode pull up/down override functional pull. |
| 5 | io_oe_n_value | R/W | 0h | IO Test mode direction, related to IO_OE_N_FORCE_CTRL |
| 4 | io_oe_n_force_ctrl | R/W | 0h | IO Test mode (alternate to BSR). The IO direction is set by IO_OE_N_VALUE and value is set by IO_CONTROL_1/2 |
| 3-0 | io_control_2 | R/W | 0h | IO_CONTROL_2 : IO reflects the value written on this register when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=0
If 0 is written, IO will be forced to ouput LOW. If 1 is written, IO will be forced to ouput HIGH. The following is the bit position for pads. 0=RX_D1; 1=RX_D2; 2=RX_D3; 3=STRP_1; |
IO_CONTROL_3 is shown in Figure 8-58 and described in Table 8-63.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_mac_rx_impedance | ||||||
| R-0h | R/W-8h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_mac_rx_impedance | RESERVED | ||||||
| R/W-8h | R/W-8h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-5 | cfg_mac_rx_impedance | R/W | 8h | Slew Rate Control for RGMII pads - 01010b = Medium Slew (OA tr/tf compliant, max tr/tf = 1ns) 01011b = Slowest Slew (For low emissions, max tr/tf = 1.2ns) 01000b = Default mode (rgmii tr/tf compliant, max tr/tf=750ps) |
| 4-0 | RESERVED | R/W | 8h | Reserved |
IO_STATUS_1 is shown in Figure 8-59 and described in Table 8-64.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| io_status_1 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| io_status_1 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | io_status_1 | R | 0h | IO_STATUS_1 : Register reflects the IO value, when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=1
If 0 is read, IO is connected LOW at pin. If 1 is read, IO is connected HIGH at pin. The following is the bit position for each pad. 0=LED_0_GPIO_0; 1=LED_1_GPIO_1; 2=CLKOUT_GPIO_2; 3=INT_N; 4=RESERVED; 5=RESERVED; 6=INH; 7=TX_CLK; 8=TX_CTRL; 9=TX_D0; 10=TX_D1; 11=TX_D2; 12=TX_D3; 13=RX_CLK; 14=RX_CTRL; 15=RX_D0; |
IO_STATUS_2 is shown in Figure 8-60 and described in Table 8-65.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | io_status_2 | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | |
| 3-0 | io_status_2 | R | 0h | IO_STATUS_2 : Register reflects the IO value, when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=1
If 0 is read, IO is connected LOW at pin. If 1 is read, IO is connected HIGH at pin. The following is the bit position for each pad. 0=RX_D1; 1=RX_D2; 2=RX_D3; 3=STRP_1; |
IO_CONTROL_4 is shown in Figure 8-61 and described in Table 8-66.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| io_input_mode | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| io_input_mode | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | io_input_mode | R/W | 0h | Each bit configures one pin into input mode as per mapping below - 0=LED_0_GPIO_0; 1=LED_1_GPIO_1; 2=CLKOUT_GPIO_2; 3=INT_N; 4=TX_CLK; 5=TX_CTRL; 6=TX_D0; 7=TX_D1; 8=TX_D2; 9=TX_D3; 10=RX_CLK; 11=RX_CTRL; 12=RX_D0; 13=RX_D1; 14=RX_D2; 15=RX_D3 |
IO_CONTROL_5 is shown in Figure 8-62 and described in Table 8-67.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| io_output_mode | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| io_output_mode | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | io_output_mode | R/W | 0h | Each bit configures one pin into output mode as per mapping below - 0=LED_0_GPIO_0; 1=LED_1_GPIO_1; 2=CLKOUT_GPIO_2; 3=INT_N; 4=TX_CLK; 5=TX_CTRL; 6=TX_D0; 7=TX_D1; 8=TX_D2; 9=TX_D3; 10=RX_CLK; 11=RX_CTRL; 12=RX_D0; 13=RX_D1; 14=RX_D2; 15=RX_D3 |
SOR_VECTOR_1 is shown in Figure 8-63 and described in Table 8-68.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RGMII_TX_SHIFT | RGMII_RX_SHIFT | SGMII_EN | RGMII_EN | TEST_MODE | MAC_MODE | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAC_MODE | MAS/SLV | PHY_AD | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RGMII_TX_SHIFT | R | 0h | 0x0 = TX shift disbaled 0x1 = TX shift enabled |
| 14 | RGMII_RX_SHIFT | R | 0h | 0x0 = RX shift disabled 0x1 = RX shift enabled |
| 13 | SGMII_EN | R | 0h | 0x0 = SGMII disabled 0x1 = SGMII enabled |
| 12 | RGMII_EN | R | 0h | 0x0 = RGMII disabled 0x1 = RGMII enabled |
| 11-9 | TEST_MODE | R | 0h | |
| 8-6 | MAC_MODE | R | 0h | 0x0 = SGMII 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved 0x4 = RGMII align 0x5 = RGMII TX shift 0x6 = RGMII TX and RX shift 0x7 = RGMII RX shift |
| 5 | MAS/SLV | R | 0h | 0x0 = Slave 0x1 = Master |
| 4-0 | PHY_AD | R | 0h | 0x0 = PHY address 0 0x4 = PHY address 4 0x5 = PHY address 5 0x8 = PHY address 8 0xA = PHY address A 0xC = PHY address C 0xD = PHY address D 0xE = PHY address E 0xF = PHY address F |
SOR_VECTOR_2 is shown in Figure 8-64 and described in Table 8-69.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AUTO/MANAGED | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | AUTO/MANAGED | R | 0h | 0x0 = Autonomous mode enabled 0x1 = Managed mode enabled |
MONITOR_CTRL1 is shown in Figure 8-65 and described in Table 8-70.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_dc_offset_2c | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_cic_gain12_arith | cfg_cic_gain2 | cfg_cic_gain1 | |||||
| R/W-0h | R/W-2h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | cfg_dc_offset_2c | R/W | 0h | Analog control |
| 7-6 | cfg_cic_gain12_arith | R/W | 0h | Analog control |
| 5-3 | cfg_cic_gain2 | R/W | 2h | Analog control |
| 2-0 | cfg_cic_gain1 | R/W | 2h | Analog control |
MONITOR_CTRL2 is shown in Figure 8-66 and described in Table 8-71.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_bypass_reset_sensor_val | cfg_rd_data | cfg_dec_factor_sensors | cfg_dec_factor_gain_calib | ||||
| R/W-0h | R/W-0h | R/W-4h | R/W-4h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_dec_factor_gain_calib | cfg_dec_factor_dc_calib | cfg_bypass_sel_num | |||||
| R/W-4h | R/W-4h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_bypass_reset_sensor_val | R/W | 0h | When cfg_bypass_fsm is 1, use this register to keep sensor in reset |
| 14-12 | cfg_rd_data | R/W | 0h | To read out monitor adc output through MDIO for debug |
| 11-9 | cfg_dec_factor_sensors | R/W | 4h | Analog control |
| 8-6 | cfg_dec_factor_gain_calib | R/W | 4h | Analog control |
| 5-3 | cfg_dec_factor_dc_calib | R/W | 4h | Analog control |
| 2-0 | cfg_bypass_sel_num | R/W | 0h | When cfg_bypass_fsm is 1, use this register to select the sensor |
MONITOR_CTRL4 is shown in Figure 8-67 and described in Table 8-72.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_hist_clr | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_discard_sample_num | cfg_avg_sample_num | cfg_adc_clk_div | cfg_force_start | cfg_reset | periodic | start | |
| R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | R/WSC-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | RESERVED |
| 8 | cfg_hist_clr | R/W | 0h | CFG_HIST_CLR |
| 7 | cfg_discard_sample_num | R/W | 1h | Number of samples to be discarded before starting averaging - 0b = 2 samples 1b = 4 samples |
| 6 | cfg_avg_sample_num | R/W | 0h | Number of samples for calculating the average before storing in history - 0b = 2 samples 1b = 4 samples |
| 5-4 | cfg_adc_clk_div | R/W | 1h | Config options to select frequency of monitor adc clock - 00b = 12.5MHz 01b = 6.25MHz 10b = 3.125MHz 11b = Reserved |
| 3 | cfg_force_start | R/W | 0h | Set to force start sensor monitor FSM even if link is not established |
| 2 | cfg_reset | R/W | 1h | 0b = Enable the monitor 1b = Monitor is held in reset state At any point of time, if the signal is changed to 1, the module abruptly goes to reset state |
| 1 | periodic | R/W | 0h | 0b = Monitor is enabled only when start is set for one iteration 1b = Monitor is enabled for periodic iteration |
| 0 | start | R/WSC | 0h | Start indication for sensor monitor FSM, self clearing |
MONITOR_STAT1 is shown in Figure 8-68 and described in Table 8-73.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| stat_rd_data | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| stat_rd_data | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | stat_rd_data | R | 0h | STAT_RD_DATA |
BREAK_LINK_TIMER is shown in Figure 8-69 and described in Table 8-74.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | cfg_fifo_reset_in_break_link | cfg_slave_send_s_32_mode | RESERVED | |||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-12Eh | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R/W-12Eh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R/W | 0h | Reserved |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12 | cfg_fifo_reset_in_break_link | R/W | 1h | Allow ADC FIFO to be in reset during break link timer |
| 11 | cfg_slave_send_s_32_mode | R/W | 0h | Enable mode where Slave PHY sends SEND_S signalling for a fixed 32 times once it has detected SEND_S
Note : Should be enabled only if 0x509[10] is not set
0h = Follow IEEE state machine 1h = Enable slave to send SEND_S 32 times |
| 10-0 | RESERVED | R/W | 12Eh | Reserved |
RS_DECODER is shown in Figure 8-70 and described in Table 8-75.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_rs_decoder_bypass | RESERVED | RESERVED | |||||
| R/W-0h | R/W-0h | R/W-2Dh | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | ||||||
| R/W-28h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_rs_decoder_bypass | R/W | 0h | Bypass RS decoder
0h = RS decoder in use 1h = Bypass RS decoder |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13-8 | RESERVED | R/W | 2Dh | Reserved |
| 7-1 | RESERVED | R/W | 28h | Reserved |
| 0 | RESERVED | R/W | 0h | Reserved |
LPS_CONTROL_1 is shown in Figure 8-71 and described in Table 8-76.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_tx_wake_cg | cfg_tx_sleep_cg | |||||
| R-0h | R/W-4h | R/W-3h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tx_sleep_cg | cfg_rx_wake_cg | cfg_rx_sleep_cg | |||||
| R/W-3h | R/W-4h | R/W-3h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-9 | cfg_tx_wake_cg | R/W | 4h | Control code to send on Tx for wake indication |
| 8-6 | cfg_tx_sleep_cg | R/W | 3h | Control code to send on Tx for sleep indication |
| 5-3 | cfg_rx_wake_cg | R/W | 4h | Control code to expect on Rx for wake indication |
| 2-0 | cfg_rx_sleep_cg | R/W | 3h | Control code to expect on Rx for sleep indication |
LPS_CONTROL_2 is shown in Figure 8-72 and described in Table 8-77.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_wake_cg_cnt_th | ||||||
| R-0h | R/W-8h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_sleep_cg_cnt_th | ||||||
| R-0h | R/W-8h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14-8 | cfg_wake_cg_cnt_th | R/W | 8h | Number of continuous expected wake code groups required to acknowledge and set LPS wake command received. |
| 7 | RESERVED | R | 0h | Reserved |
| 6-0 | cfg_sleep_cg_cnt_th | R/W | 8h | Number of continuous expected sleep code groups required to acknowledge and set LPS sleep command received. |
MAXWAIT_TIMER is shown in Figure 8-73 and described in Table 8-78.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_maxwait_timer_init | |||||||
| R/W-17CEh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_maxwait_timer_init | |||||||
| R/W-17CEh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | cfg_maxwait_timer_init | R/W | 17CEh | Maxwait timer (used during link-up) : value in us = decimal value multipled by 16 |
PHY_CTRL_1G is shown in Figure 8-74 and described in Table 8-79.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | cfg_force_link_stat_val | cfg_force_link_stat | RESERVED | RESERVED |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_minwait_timer_init | |||||||
| R/W-3Dh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14 | RESERVED | R/W | 0h | Reserved |
| 13 | RESERVED | R/W | 0h | Reserved |
| 12 | RESERVED | R/W | 0h | Reserved |
| 11 | cfg_force_link_stat_val | R/W | 0h | Forced link status value Valid only if 0x519[10] is set |
| 10 | cfg_force_link_stat | R/W | 0h | Enable forcing link status value |
| 9 | RESERVED | R/W | 0h | Reserved |
| 8 | RESERVED | R/W | 0h | Reserved |
| 7-0 | cfg_minwait_timer_init | R/W | 3Dh | Minwait timer (used during link-up) : value in us = decimal value multipled by 16 |
TEST_MODE is shown in Figure 8-75 and described in Table 8-80.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_test_mode4_tx_order | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_test_mode_7_data | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | cfg_test_mode4_tx_order | R/W | 0h | Order of symbols to be transmitted in Test mode 4
0h = T1 followed by T2 1h = T2 followed by T1 |
| 7-0 | cfg_test_mode_7_data | R/W | 0h | GMII data to transmit in Test mode 7 |
LINK_QUAL_1 is shown in Figure 8-76 and described in Table 8-81.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| link_training_time | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | link_training_time | R | 0h | Link training time in ms (TC12) |
LINK_QUAL_2 is shown in Figure 8-77 and described in Table 8-82.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| remote_receiver_time | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| local_receiver_time | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | remote_receiver_time | R | 0h | Remote receiver time in ms (TC12) |
| 7-0 | local_receiver_time | R | 0h | Local receiver time in ms (TC12) |
LINK_DOWN_LATCH_STAT is shown in Figure 8-78 and described in Table 8-83.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | channel_ok_ll | link_fail_inhibit_lh | send_s_sigdet_lh | hi_rfer_lh | block_lock_ll | pma_watchdog_ll | |
| R-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | R/W0S-0h | R/W0S-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-6 | RESERVED | R | 0h | Reserved |
| 5 | channel_ok_ll | R/W0C | 0h | 1b = Channel ok was never de-asserted 0b = Channel ok was de-asserted |
| 4 | link_fail_inhibit_lh | R/W0C | 0h | 1b = Link fail inhibit assertion was reported 0b = Link fail inhibit assertion was never reported |
| 3 | send_s_sigdet_lh | R/W0C | 0h | 1b = Send s sigdet assertion was reported 0b = Send s sigdet assertion was never reported |
| 2 | hi_rfer_lh | R/W0C | 0h | 1b = High ri rfer assertion was reported 0b = High ri rfer assertion was never reported |
| 1 | block_lock_ll | R/W0S | 0h | 1b = Block lock de-assertion was never reported 0b = Block lock de-assertion was never reported |
| 0 | pma_watchdog_ll | R/W0S | 0h | 1b = Low pma watchdog was never reported 0b = Low pma watchdof was reported |
LINK_QUAL_3 is shown in Figure 8-79 and described in Table 8-84.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| link_loss_cnt | link_fail_cnt | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| link_fail_cnt | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | link_loss_cnt | R | 0h | Link loss count since last power cycle (TC12) |
| 9-0 | link_fail_cnt | R | 0h | Link fail without link loss count since last power cycle (TC12) |
LINK_QUAL_4 is shown in Figure 8-80 and described in Table 8-85.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | comm_ready | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | comm_ready | R | 0h | Communication ready status (TC12) |
RS_DECODER_FRAME_STAT_2 is shown in Figure 8-81 and described in Table 8-86.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rs_dec_uncorr_frame_cnt | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rs_dec_uncorr_frame_cnt | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rs_dec_uncorr_frame_cnt | 0h | No of uncorrectable RS frames received at RS decoder, clear on read, saturates |
PMA_WATCHDOG is shown in Figure 8-82 and described in Table 8-87.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_pma_watchdog_force_val | cfg_pma_watchdog_force_en | cfg_ieee_watchdog_en | cfg_watchdog_cnt_clr_th | |||
| R-0h | R/W-1h | R/W-0h | R/W-1h | R/W-1h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | cfg_pma_watchdog_force_val | R/W | 1h | Force value for pma watchdog |
| 5 | cfg_pma_watchdog_force_en | R/W | 0h | Enable forcing pma watchdog |
| 4 | cfg_ieee_watchdog_en | R/W | 1h | 1 : watchdog counters are started after link up 0: TBD |
| 3-0 | cfg_watchdog_cnt_clr_th | R/W | 1h | Number of 0, +1, -1 symbols to be seen in their respective watchdog counter window to prevent them for asserting pma_watchdog_status |
SYMB_POL_CFG is shown in Figure 8-83 and described in Table 8-88.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_slave_auto_pol_correction_en | cfg_rx_symb_order_inv | cfg_rx_symb_pol_inv | cfg_tx_symb_order_inv | cfg_tx_symb_pol_inv | ||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-5 | RESERVED | R | 0h | Reserved |
| 4 | cfg_slave_auto_pol_correction_en | R/W | 0h | Correct tx polarity for slave based on received polarity
0h = Slave tx polarity independent of slave rx polarity 1h = Slave tx polarity to match received polarity |
| 3 | cfg_rx_symb_order_inv | R/W | 0h | Order of received symbols S0 to S6 reversed to S6 to S0
Valid only if LPs 0x55B[1] is set (TI-TI link)
0h = Order of received symbols S0 to S6 unchanged 1h = Order of received symbols S0 to S6 reversed to S6 to S0 |
| 2 | cfg_rx_symb_pol_inv | R/W | 0h | Invert polarity of received symbols
0h = Unchanged polarity of received symbols 1h = Invert polarity of received symbols |
| 1 | cfg_tx_symb_order_inv | R/W | 0h | Order of transmit symbols S0 to S6 reversed to S6 to S0
Valid only if LPs 0x55B[3] is set (TI-TI link)
0h = Order of transmit symbols S0 to S6 unchanged 1h = Order of transmit symbols S0 to S6 reversed to S6 to S0 |
| 0 | cfg_tx_symb_pol_inv | R/W | 0h | Invert polarity of transmit symbols
0h = Unchanged polarity of transmit symbols 1h = Invert polarity of transmit symbols |
OAM_CFG is shown in Figure 8-84 and described in Table 8-89.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_rx_oam_crc_data_in_order | cfg_tx_oam_crc_data_in_order | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | cfg_rx_oam_crc_data_in_order | R/W | 0h | Reverse order of data input to CRC checker in rx oam to MSB first
0h = Order of data input to CRC checker in rx oam is LSB first 1h = Order of data input to CRC checker in rx oam is MSB first |
| 0 | cfg_tx_oam_crc_data_in_order | R/W | 0h | Reverse order of data input to CRC calculator in tx oam to MSB first
0h = Order of data input to CRC calculator in tx oam is LSB first 1h = Order of data input to CRC calculator in tx oam is MSB first |
TEST_MEM_CFG is shown in Figure 8-85 and described in Table 8-90.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_wait_time_xcorr_wen | ||||||
| R-0h | R/W-5Eh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_wait_time_xcorr_wen | cfg_xcorr_dbg_sel | cfg_send_s_infinite_loop | cfg_xcorr_dbg_test_mem | cfg_ecc_en | cfg_test_mem_sigdet_debug | cfg_pcs_test_mem_mode | |
| R/W-5Eh | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-6 | cfg_wait_time_xcorr_wen | R/W | 5Eh | Wait timer after TX_SEND_S after which testmem is written on energy fall Note : Valid only if 0x561[3] is set |
| 5 | cfg_xcorr_dbg_sel | R/W | 1h | 0b = Select xcorr from aligned detector to write to test mem 1b = Select xcorr from shifted detector to write to test mem Note : Valid only if 0x561[3] is set |
| 4 | cfg_send_s_infinite_loop | R/W | 0h | enable transmitting infinite send_s sequence. For send_s debug.
Valid only in master and when 0x56A[15] is set.
0h = disable infinte send_s mode 1h = enable infinite send_s mode |
| 3 | cfg_xcorr_dbg_test_mem | R/W | 0h | enabled xcorr debug for send_s.
Valid only if 0x561[0] is 1b0
0h = Normal send_s debug. Refer to 0x561[1] 1h = Enabled xcorr debug |
| 2 | cfg_ecc_en | R/W | 0h | Enable ECC logic for RS decoder memory
0h = ECC encoding/decoding is disabled 1h = ECC encoding/decoding is enabled |
| 1 | cfg_test_mem_sigdet_debug | R/W | 0h | Enable sidget debug mode in test mem send s mode
Valid only if 0x561[0] is 1b0
0h = Test mem written in send s mode only on state transition 1h = Enable sigdet debug mode in test mem send s mode |
| 0 | cfg_pcs_test_mem_mode | R/W | 0h | Choose send s or train rx test mem mode
0h = Send s info on test mem 1h = Train rx info on test mem |
FORCE_CTRL1 is shown in Figure 8-86 and described in Table 8-91.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_force_link_sync_state_en | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_force_link_sync_state_val | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | cfg_force_link_sync_state_en | R/W | 0h | Force link sync state enable |
| 7-0 | cfg_force_link_sync_state_val | R/W | 0h | Force link sync state value |
RGMII_CTRL is shown in Figure 8-87 and described in Table 8-92.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | rgmii_rx_half_full_th | ||||||
| R-0h | R/W-2h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rgmii_rx_half_full_th | rgmii_tx_half_full_th | rgmii_tx_if_en | invert_rgmii_txd | invert_rgmii_rxd | sup_tx_err_fd | ||
| R/W-2h | R/W-2h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-7 | rgmii_rx_half_full_th | R/W | 2h | RGMII RX sync FIFO half full threshold |
| 6-4 | rgmii_tx_half_full_th | R/W | 2h | RGMII TX sync FIFO half full threshold |
| 3 | rgmii_tx_if_en | R/W | 0h | RGMII enable bit
Default from strap
0h = RGMII disable 1h = RGMII enable |
| 2 | invert_rgmii_txd | R/W | 0h | Invert RGMII Tx wire order - full swap [3:0] to [0:3]
0h = Keep RGMII Tx wire order same - [3: 1h = Invert RGMII Tx wire order - [3: |
| 1 | invert_rgmii_rxd | R/W | 0h | Invert RGMII Rx wire order - full swap [3:0] to [0:3]
0h = Keep RGMII Rx wire order same - [3: 1h = Invert RGMII Rx wire order - [3: |
| 0 | sup_tx_err_fd | R/W | 0h | 1: suppress tx_err in full duplex mode when tx_en set to zero 0: allow tx_err assertion to PHY when tx_en set to zero (this bit can disable the TX_ERR indication input) |
RGMII_FIFO_STATUS is shown in Figure 8-88 and described in Table 8-93.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rgmii_rx_af_full_err | rgmii_rx_af_empty_err | rgmii_tx_af_full_err | rgmii_tx_af_empty_err | |||
| R-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | rgmii_rx_af_full_err | R/W0C | 0h | RGMII RX fifo full error
0h = No empty fifo error 1h = RGMII TX full error has been indicated |
| 2 | rgmii_rx_af_empty_err | R/W0C | 0h | RGMII RX fifo empty error
0h = No empty fifo error 1h = RGMII RX empty error has been indicated |
| 1 | rgmii_tx_af_full_err | R/W0C | 0h | RGMII TX fifo full error
0h = No empty fifo error 1h = RGMII TX full error has been indicated |
| 0 | rgmii_tx_af_empty_err | R/W0C | 0h | RGMII TX fifo empty error
0h = No empty fifo error 1h = RGMII TX empty error has been indicated |
RGMII_DELAY_CTRL is shown in Figure 8-89 and described in Table 8-94.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rx_clk_sel | tx_clk_sel | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | rx_clk_sel | R/W | 0h | In RGMII mode, Enable or disable the internal delay for RXD wrt RX_CLK (use this mode when RGMII_RX_CLK and RGMII_RXD are aligned). The delay magnitude can be configured by programming register 0x430[7:4]
0h = clock and data are aligned 1h = clock on PIN is delayed by 90 degrees relative to RGMII_RX data |
| 0 | tx_clk_sel | R/W | 0h | In RGMII mode, Enable or disable the internal delay for TXD wrt TX_CLK (use this mode when RGMII_TX_CLK and RGMII_TXD are aligned). The delay magnitude can be configured by programming register 0x430[11:8]
0h = clock and data are aligned 1h = clock is internally delayed by 90 degrees |
SGMII_CTRL_1 is shown in Figure 8-90 and described in Table 8-95.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| sgmii_tx_err_dis | cfg_align_idx_force | cfg_align_idx_value | cfg_sgmii_en | cfg_sgmii_rx_pol_invert | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_sgmii_tx_pol_invert | RESERVED | RESERVED | RESERVED | sgmii_autoneg_timer | mr_an_enable | ||
| R/W-0h | R/W-3h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | sgmii_tx_err_dis | R/W | 0h | 1 = Disable SGMII TX Error indication 0 = Enable SGMII TX Error indication |
| 14 | cfg_align_idx_force | R/W | 0h | Force word boundray index selection |
| 13-10 | cfg_align_idx_value | R/W | 0h | when cfg_align_idx_force = 1 This value set the iword boundray index |
| 9 | cfg_sgmii_en | R/W | 0h | SGMII enable bit
Default from strap
0h = SGMII disable 1h = SGMII enable |
| 8 | cfg_sgmii_rx_pol_invert | R/W | 0h | SGMII RX bus invert polarity
0h = Polarity not inverted 1h = SGMII RX bus invert polarity |
| 7 | cfg_sgmii_tx_pol_invert | R/W | 0h | SGMII TX bus invert polarity
0h = Polarity not inverted 1h = SGMII TX bus invert polarity |
| 6-5 | RESERVED | R/W | 3h | Reserved |
| 4 | RESERVED | R/W | 1h | Reserved |
| 3 | RESERVED | R/W | 1h | Reserved |
| 2-1 | sgmii_autoneg_timer | R/W | 1h | Selects duration of SGMII Auto-Negotiation timer: 00: 1.6ms 01: 2us 10: 800us 11: 11ms |
| 0 | mr_an_enable | R/W | 1h | 1 = Enable SGMII Auto-Negotaition 0 = Disable SGMII Auto-Negotiation |
SGMII_STATUS is shown in Figure 8-91 and described in Table 8-96.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | sgmii_page_received | link_status_1000bx | mr_an_complete | cfg_align_en | cfg_sync_status | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_align_idx | cfg_state | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12 | sgmii_page_received | R | 0h | Indicates that a new auto neg page was received
0h = No new auto neg page received 1h = A new auto neg page received |
| 11 | link_status_1000bx | R | 0h | sgmii link status
0h = SGMII link down 1h = SGMII link up |
| 10 | mr_an_complete | R | 0h | sgmii autoneg complete indication
0h = SGMII autoneg not completed 1h = SGMII autoneg completed |
| 9 | cfg_align_en | R | 0h | word boundary FSM - align indication |
| 8 | cfg_sync_status | R | 0h | word boundary FSM - sync status indication
0h = sync not achieved 1h = sync achieved |
| 7-4 | cfg_align_idx | R | 0h | word boundary index selection |
| 3-0 | cfg_state | R | 0h | word boundary FSM state |
SGMII_CTRL_2 is shown in Figure 8-92 and described in Table 8-97.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | sgmii_signal_detect_force_val | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sgmii_signal_detect_force_en | mr_restart_an | tx_half_full_th | rx_half_full_th | ||||
| R/W-0h | R/WSC,0-0h | R/W-3h | R/W-3h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8 | sgmii_signal_detect_force_val | R/W | 0h | SGMII cdr lock force value |
| 7 | sgmii_signal_detect_force_en | R/W | 0h | SGMII cdr lock force enable |
| 6 | mr_restart_an | R/WSC,0 | 0h | Restart sgmii autonegotiation |
| 5-3 | tx_half_full_th | R/W | 3h | SGMII TX sync FIFO half full threshold |
| 2-0 | rx_half_full_th | R/W | 3h | SGMII RX sync FIFO half full threshold |
SGMII_FIFO_STATUS is shown in Figure 8-93 and described in Table 8-98.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | sgmii_rx_af_full_err | sgmii_rx_af_empty_err | sgmii_tx_af_full_err | sgmii_tx_af_empty_err | |||
| R-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | R/W0C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | sgmii_rx_af_full_err | R/W0C | 0h | SGMII RX fifo full error
0h = No error indication 1h = SGMII RX fifo full error has been indicated |
| 2 | sgmii_rx_af_empty_err | R/W0C | 0h | SGMII RX fifo empty error
0h = No error indication 1h = SGMII RX fifo empty error has been indicated |
| 1 | sgmii_tx_af_full_err | R/W0C | 0h | SGMII TX fifo full error
0h = No error indication 1h = SGMII TX fifo full error has been indicated |
| 0 | sgmii_tx_af_empty_err | R/W0C | 0h | SGMII TX fifo empty error
0h = No error indication 1h = SGMII TX fifo empty error has been indicated |
PRBS_STATUS_1 is shown in Figure 8-94 and described in Table 8-99.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_err_ov_cnt | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | prbs_err_ov_cnt | R | 0h | Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active |
PRBS_CTRL_1 is shown in Figure 8-95 and described in Table 8-100.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_pkt_gen_64 | send_pkt | RESERVED | cfg_prbs_chk_sel | |||
| R-0h | R/W-0h | R/WMC,0-0h | R-0h | R/W-5h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_prbs_gen_sel | cfg_prbs_cnt_mode | cfg_prbs_chk_enable | cfg_pkt_gen_prbs | pkt_gen_en | ||
| R-0h | R/W-7h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13 | cfg_pkt_gen_64 | R/W | 0h | Reserved |
| 12 | send_pkt | R/WMC,0 | 0h | Enables generating MAC packet with fix/incremental data w CRC
(pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear)
Cleared automatically when pkt_done is set
0h = Stop MAC packet 1h = Transmit MAC packet w CRC |
| 11 | RESERVED | R | 0h | Reserved |
| 10-8 | cfg_prbs_chk_sel | R/W | 5h | 000 : Checker receives from RGMII TX 001 : Checker receives SGMII TX 101 : Checker receives from Cu RX |
| 7 | RESERVED | R | 0h | Reserved |
| 6-4 | cfg_prbs_gen_sel | R/W | 7h | 000 : PRBS transmits to RGMII RX 001 : PRBS transmits to SGMII RX 101 : PRBS transmits to Cu TX |
| 3 | cfg_prbs_cnt_mode | R/W | 0h | 1 = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again 0 = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting. |
| 2 | cfg_prbs_chk_enable | R/W | 1h | Enable PRBS checker xbar (to receive data)
To be enabled for counters in 0x63C, 0x63D, 0x63E to work
0h = Disable PRBS checker 1h = Enable PRBS checker |
| 1 | cfg_pkt_gen_prbs | R/W | 0h | If set:
(1) When pkt_gen_en is set, PRBS packets are generated continuously
(3) When pkt_gen_en is cleared, PRBS RX checker is still enabled
If cleared:
(1) When pkt_gen_en is set, non - PRBS packet is generated
(3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well
0h = Stop PRBS packet 1h = Transmit PRBS packet |
| 0 | pkt_gen_en | R/W | 0h | 1 = Enable packet/PRBS generator 0 = Disable packet/PRBS generator |
PRBS_CTRL_2 is shown in Figure 8-96 and described in Table 8-101.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_pkt_len_prbs | |||||||
| R/W-5DCh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_pkt_len_prbs | |||||||
| R/W-5DCh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | cfg_pkt_len_prbs | R/W | 5DCh | Length (in bytes) of PRBS packets and MAC packets w CRC |
PRBS_CTRL_3 is shown in Figure 8-97 and described in Table 8-102.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_ipg_len | |||||||
| R/W-7Dh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | cfg_ipg_len | R/W | 7Dh | Inter-packet gap (in bytes) between packets |
PRBS_STATUS_2 is shown in Figure 8-98 and described in Table 8-103.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_byte_cnt | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_byte_cnt | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_byte_cnt | R | 0h | Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF |
PRBS_STATUS_3 is shown in Figure 8-99 and described in Table 8-104.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_pkt_cnt_15_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_pkt_cnt_15_0 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_pkt_cnt_15_0 | R | 0h | Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_4 is shown in Figure 8-100 and described in Table 8-105.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_pkt_cnt_31_16 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_pkt_cnt_31_16 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_pkt_cnt_31_16 | R | 0h | Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_6 is shown in Figure 8-101 and described in Table 8-106.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | pkt_done | pkt_gen_busy | prbs_pkt_ov | prbs_byte_ov | prbs_lock | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_err_cnt | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12 | pkt_done | R | 0h | Set when all MAC packets w CRC are transmitted
0h = MAC packet transmission in progress 1h = MAC packets transmission completed |
| 11 | pkt_gen_busy | R | 0h | 1 = Packet generator is in process 0 = Packet generator is not in process |
| 10 | prbs_pkt_ov | R | 0h | If set, packet counter reached overflow
Overflow is cleared when PRBS counters are cleared - done by setting bit #1 of prbs_status_6
0h = No overflow 1h = Packet counter overflow |
| 9 | prbs_byte_ov | R | 0h | If set, bytes counter reached overflow
Overflow is cleared when PRBS counters are cleared - done by setting bit #1of prbs_status_6
0h = No overflow 1h = byte counter overflow |
| 8 | prbs_lock | R | 0h | 1 = PRBS checker is locked sync) on received byte stream
0 = PRBS checker is not locked
0h = PRBS checker is not locked 1h = PRBS checker is locked sync) on received byte stream |
| 7-0 | prbs_err_cnt | R | 0h | Holds number of errored bits received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters |
PRBS_STATUS_8 is shown in Figure 8-102 and described in Table 8-107.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pkt_err_cnt_15_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pkt_err_cnt_15_0 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pkt_err_cnt_15_0 | R | 0h | Bits [15:0] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_9 is shown in Figure 8-103 and described in Table 8-108.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pkt_err_cnt_31_16 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pkt_err_cnt_31_16 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pkt_err_cnt_31_16 | R | 0h | Bits [31:16] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_CTRL_4 is shown in Figure 8-104 and described in Table 8-109.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_pkt_data | |||||||
| R/W-55h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_pkt_mode | cfg_pattern_vld_bytes | cfg_pkt_cnt | |||||
| R/W-0h | R/W-2h | R/W-1h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | cfg_pkt_data | R/W | 55h | Fixed data to be sent in Fix data mode |
| 7-6 | cfg_pkt_mode | R/W | 0h | 2b00 - Incremental
2b01 - Fixed
2b1x - PRBS
0h = Incremental 1h = Fixed |
| 5-3 | cfg_pattern_vld_bytes | R/W | 2h | Number of bytes of valid pattern in packet (Max - 6)
0h = 0 bytes 1h = 1 bytes 2h = 2 bytes 3h = 3 bytes 4h = 4 bytes 5h = 5 bytes 6h = 6 bytes 7h = 6 bytes |
| 2-0 | cfg_pkt_cnt | R/W | 1h | 000b = 1 packet
001b = 10 packets
010b = 100 packets
011b = 1000 packets
100b = 10000 packets
101b = 100000 packets
110b = 1000000 packets
111b = Continuous packets
0h = 1 packet 1h = 10 packets 2h = 100 packets 3h = 1000 packets 4h = 10000 packets 5h = 100000 packets 6h = 1000000 packets 7h = Continuous packets |
PRBS_CTRL_5 is shown in Figure 8-105 and described in Table 8-110.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_15_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_15_0 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_15_0 | R/W | 0h | Bits 15:0 of pattern |
PRBS_CTRL_6 is shown in Figure 8-106 and described in Table 8-111.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_31_16 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_31_16 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_31_16 | R/W | 0h | Bits 31:16 of pattern |
PRBS_CTRL_7 is shown in Figure 8-107 and described in Table 8-112.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_47_32 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_47_32 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_47_32 | R/W | 0h | Bits 47:32 of pattern |
PRBS_CTRL_8 is shown in Figure 8-108 and described in Table 8-113.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_15_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_15_0 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_15_0 | R/W | 0h | Bits 15:0 of Perfect Match Data - used for DA (destination address) match |
PRBS_CTRL_9 is shown in Figure 8-109 and described in Table 8-114.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_31_16 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_31_16 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_31_16 | R/W | 0h | Bits 31:16 of Perfect Match Data - used for DA (destination address) match |
PRBS_CTRL_10 is shown in Figure 8-110 and described in Table 8-115.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_47_32 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_47_32 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_47_32 | R/W | 0h | Bits 47:32 of Perfect Match Data - used for DA (destination address) match |
CRC_STATUS is shown in Figure 8-111 and described in Table 8-116.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rx_bad_crc | tx_bad_crc | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | rx_bad_crc | R | 0h | CRC error indication in packet received on Cu RX
0h = No CRC error 1h = CRC error |
| 0 | tx_bad_crc | R | 0h | CRC error indication in packet transmitted on Cu TX
0h = No CRC error 1h = CRC error |
PKT_STAT_1 is shown in Figure 8-112 and described in Table 8-117.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_pkt_cnt_15_0 | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_pkt_cnt_15_0 | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_pkt_cnt_15_0 | 0h | Lower 16 bits of Tx packet counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence |
PKT_STAT_2 is shown in Figure 8-113 and described in Table 8-118.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_pkt_cnt_31_16 | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_pkt_cnt_31_16 | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_pkt_cnt_31_16 | 0h | Upper 16 bits of Tx packet counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence |
PKT_STAT_3 is shown in Figure 8-114 and described in Table 8-119.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_err_pkt_cnt | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_err_pkt_cnt | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_err_pkt_cnt | 0h | Tx packet w error (CRC error) counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence |
PKT_STAT_4 is shown in Figure 8-115 and described in Table 8-120.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_pkt_cnt_15_0 | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_pkt_cnt_15_0 | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_pkt_cnt_15_0 | 0h | Lower 16 bits of Rx packet counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence |
PKT_STAT_5 is shown in Figure 8-116 and described in Table 8-121.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_pkt_cnt_31_16 | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_pkt_cnt_31_16 | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_pkt_cnt_31_16 | 0h | Upper 16 bits of Rx packet counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence |
PKT_STAT_6 is shown in Figure 8-117 and described in Table 8-122.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_err_pkt_cnt | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_err_pkt_cnt | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_err_pkt_cnt | 0h | Rx packet w error (CRC error) counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence |
SQI_REG_1 is shown in Figure 8-118 and described in Table 8-123.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| worst_sqi_out | RESERVED | sqi_out | RESERVED | ||||
| 0h | R-0h | R-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-5 | worst_sqi_out | 0h | 3 bit Worst SQI since last read (see SQI mapping above) | |
| 4 | RESERVED | R | 0h | Reserved |
| 3-1 | sqi_out | R | 0h | 3 bit SQI - (mse here refers to Mean Square Error 0x875[9:0]) 0b000 = MSE > 102 0b001 = 81 < MSE ≤102 0b010 = 65 < MSE ≤ 81 0b011 = 51 < MSE ≤ 65 0b100 = 41 < MSE ≤ 51 0b101 = 32 < MSE ≤ 41 0b110 = 25 < MSE ≤ 32 0b111 = MSE ≤ 25 |
| 0 | RESERVED | R | 0h | Reserved |
DSP_REG_75 is shown in Figure 8-119 and described in Table 8-124.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | mse_lock | |||||
| R-0h | R-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mse_lock | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-10 | RESERVED | R | 0h | Reserved |
| 9-0 | mse_lock | R | 0h | 10 bit mse used for SQI mapping. (mse = mean square error at the receiver) |
SQI_1 is shown in Figure 8-120 and described in Table 8-125.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_hist_1_2 | cfg_acc_window_sel | cfg_sqi_th_1_2 | |||||
| R/W-3h | R/W-0h | R/W-51h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_sqi_th_1_2 | |||||||
| R/W-51h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | cfg_hist_1_2 | R/W | 3h | Hysteresis between SQI value 1 and 2 |
| 11-10 | cfg_acc_window_sel | R/W | 0h | Accumulator window select - 00b = 90us 01b = 180us 10b = 360us 11b = 720us |
| 9-0 | cfg_sqi_th_1_2 | R/W | 51h | Threshold between SQI value 1 and 2 |
PMA_PMD_CONTROL_1 is shown in Figure 8-121 and described in Table 8-126.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pma_reset_2 | RESERVED | cfg_low_power_2 | RESERVED | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | pma_reset_2 | R | 0h | 1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing |
| 14-12 | RESERVED | R | 0h | Reserved |
| 11 | cfg_low_power_2 | R | 0h | 1 = Low-power mode 0 = Normal operation Note - RW bit |
| 10-0 | RESERVED | R | 0h | Reserved |
PMA_PMD_CONTROL_2 is shown in Figure 8-122 and described in Table 8-127.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_pma_type_selection | ||||||
| R-0h | R/W-3Dh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-6 | RESERVED | R | 0h | Reserved |
| 5-0 | cfg_pma_type_selection | R/W | 3Dh | BASE-T1 type selection for device
3Dh = BASE-T1 type selection for device |
PMA_PMD_TRANSMIT_DISABLE is shown in Figure 8-123 and described in Table 8-128.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_transmit_disable_2 | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | cfg_transmit_disable_2 | R | 0h | 1 = Transmit disable 0 = Normal operation Note - RW bit |
PMA_PMD_EXTENDED_ABILITY2 is shown in Figure 8-124 and described in Table 8-129.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | base_t1_extended_abilities | RESERVED | |||||
| R-0h | R-1h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11 | base_t1_extended_abilities | R | 1h | 1 = PMA/PMD has BASE-T1 extended abilities listed in register 1.18 0 = PMA/PMD does not have BASE-T1 extended abilities |
| 10-0 | RESERVED | R | 0h | Reserved |
PMA_PMD_EXTENDED_ABILITY is shown in Figure 8-125 and described in Table 8-130.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | mr_1000_base_t1_ability | mr_100_base_t1_ability | |||||
| R-0h | R-1h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | mr_1000_base_t1_ability | R | 1h | 1 = PMA/PMD is able to perform 1000BASE-T1 0 = PMA/PMD is not able to perform 1000BASE-T1 |
| 0 | mr_100_base_t1_ability | R | 0h | 1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not able to perform 100BASE-T1 |
PMA_PMD_CONTROL is shown in Figure 8-126 and described in Table 8-131.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_master_slave_val | RESERVED | |||||
| R-1h | R/W-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | ||||||
| R-0h | R/W-1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 1h | Reserved |
| 14 | cfg_master_slave_val | R/W | 0h | 1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE |
| 13-4 | RESERVED | R | 0h | Reserved |
| 3-0 | RESERVED | R/W | 1h | Reserved |
PMA_CONTROL is shown in Figure 8-127 and described in Table 8-132.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pma_reset | cfg_transmit_disable | RESERVED | cfg_low_power | RESERVED | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | pma_reset | R | 0h | 1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing |
| 14 | cfg_transmit_disable | R | 0h | 1 = Transmit disable 0 = Normal operation Note - RW bit |
| 13-12 | RESERVED | R | 0h | Reserved |
| 11 | cfg_low_power | R | 0h | 1 = Low-power mode 0 = Normal operation Note - RW bit |
| 10-0 | RESERVED | R | 0h | Reserved |
PMA_STATUS is shown in Figure 8-128 and described in Table 8-133.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | oam_ability | eee_ability | receive_fault_ability | low_power_ability | |||
| R-0h | R-1h | R-0h | R-0h | R-1h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | receive_polarity | receive_fault | pma_receive_link_status_ll | ||||
| R-0h | R-0h | R-0h | R/W0S-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11 | oam_ability | R | 1h | 1 = PHY has 1000BASE-T1 OAM ability 0 = PHY does not have 1000BASE-T1 OAM ability |
| 10 | eee_ability | R | 0h | 1 = PHY has EEE ability 0 = PHY does not have EEE ability |
| 9 | receive_fault_ability | R | 0h | 1 = PMA/PMD has the ability to detect a fault condition on the receive path 0 = PMA/PMD does not have the ability to detect a fault condition on the receive path |
| 8 | low_power_ability | R | 1h | 1 = PMA/PMD has low-power ability 0 = PMA/PMD does not have low-power ability |
| 7-3 | RESERVED | R | 0h | Reserved |
| 2 | receive_polarity | R | 0h | 1 = Receive polarity is reversed 0 = Receive polarity is not reversed |
| 1 | receive_fault | R | 0h | 1 = Fault condition detected 0 = Fault condition not detected |
| 0 | pma_receive_link_status_ll | R/W0S | 0h | 1 = PMA/PMD receive link up 0 = PMA/PMD receive link down |
TRAINING is shown in Figure 8-129 and described in Table 8-134.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_training_user_fld | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_training_user_fld | RESERVED | cfg_oam_en | cfg_eee_en | ||||
| R/W-0h | R-0h | R/W-1h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10-4 | cfg_training_user_fld | R/W | 0h | 7-bit user defined field to send to the link partner |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1 | cfg_oam_en | R/W | 1h | 1 = 1000BASE-T1 OAM ability advertised to link partner 0 = 1000BASE-T1 OAM ability not advertised to link partner |
| 0 | cfg_eee_en | R/W | 0h | 1 = EEE ability advertised to link partner 0 = EEE ability not advertised to link partner |
LP_TRAINING is shown in Figure 8-130 and described in Table 8-135.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | lp_training_user_fld | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| lp_training_user_fld | RESERVED | lp_oam_adv | lp_eee_adv | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10-4 | lp_training_user_fld | R | 0h | 7-bit user defined field received from the link partner |
| 3-2 | RESERVED | R | 0h | Reserved |
| 1 | lp_oam_adv | R | 0h | 1 = Link partner has 1000BASE-T1 OAM ability 0 = Link partner does not have 1000BASE-T1 OAM ability |
| 0 | lp_eee_adv | R | 0h | 1 = Link partner has EEE ability 0 = Link partner does not have EEE ability |
TEST_MODE_CONTROL is shown in Figure 8-131 and described in Table 8-136.
Return to the Summary Table.
First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_test_mode | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | cfg_test_mode | R/W | 0h | 111 = Test mode 7 110 = Test mode 6 101 = Test mode 5 100 = Test mode 4 011 = Reserved 010 = Test mode 2 001 = Test mode 1 000 = Normal (non-test) operation |
| 12-0 | RESERVED | R | 0h | Reserved |
PCS_CONTROL_COPY is shown in Figure 8-132 and described in Table 8-137.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pcs_reset_2 | mmd3_loopback_2 | RESERVED | |||||
| R-0h | R-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | pcs_reset_2 | R | 0h | Note - RW bit, self clear bit
0h = Normal operation 1h = PCS reset |
| 14 | mmd3_loopback_2 | R | 0h | Note - RW bit
0h = Disable loopback mode 1h = Enable loopback mode |
| 13-0 | RESERVED | R | 0h | Reserved |
PCS_CONTROL is shown in Figure 8-133 and described in Table 8-138.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pcs_reset | mmd3_loopback | RESERVED | |||||
| R-0h | R-0h | R-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | pcs_reset | R | 0h | Note - RW bit, self clear bit
0h = Normal operation 1h = PCS reset |
| 14 | mmd3_loopback | R | 0h | Note - RW bit
0h = Disable loopback mode 1h = Enable loopback mode |
| 13-0 | RESERVED | R | 0h | Reserved |
PCS_STATUS is shown in Figure 8-134 and described in Table 8-139.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | tx_lpi_received_lh | rx_lpi_received_lh | tx_lpi_indication | rx_lpi_indication | |||
| R-0h | R/W0C-0h | R/W0C-0h | R-0h | R-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pcs_fault | RESERVED | pcs_receive_link_status_ll | RESERVED | ||||
| R-0h | R-0h | R/W0S-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11 | tx_lpi_received_lh | R/W0C | 0h | 0h = LPI not received 1h = Tx PCS has received LPI |
| 10 | rx_lpi_received_lh | R/W0C | 0h | 0h = LPI not received 1h = Rx PCS has received LPI |
| 9 | tx_lpi_indication | R | 0h | 0h = PCS is not currently receiving LPI 1h = Tx PCS is currently receiving LPI |
| 8 | rx_lpi_indication | R | 0h | 0h = PCS is not currently receiving LPI 1h = Rx PCS is currently receiving LPI |
| 7 | pcs_fault | R | 0h | 0h = No fault condition detected 1h = Fault condition detected |
| 6-3 | RESERVED | R | 0h | Reserved |
| 2 | pcs_receive_link_status_ll | R/W0S | 0h | 0h = PCS receive link down 1h = PCS receive link up |
| 1-0 | RESERVED | R | 0h | Reserved |
PCS_STATUS_2 is shown in Figure 8-135 and described in Table 8-140.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | pcs_receive_link_status | hi_rfer | block_lock | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| hi_rfer_lh | block_lock_ll | RESERVED | |||||
| R/W0C-0h | R/W0S-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | pcs_receive_link_status | R | 0h | 0h = PCS receive link down 1h = PCS receive link up |
| 9 | hi_rfer | R | 0h | 0h = PCS not reporting a high BER 1h = PCS reporting a high BER |
| 8 | block_lock | R | 0h | 0h = PCS not locked to received blocks 1h = PCS locked to received blocks |
| 7 | hi_rfer_lh | R/W0C | 0h | 0h = PCS has not reported a high BER 1h = PCS has reported a high BER |
| 6 | block_lock_ll | R/W0S | 0h | 0h = PCS does not have block lock 1h = PCS has block lock |
| 5-0 | RESERVED | R | 0h | Reserved |
OAM_TRANSMIT is shown in Figure 8-136 and described in Table 8-141.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_tx_valid | mr_tx_toggle | mr_tx_received | mr_tx_received_toggle | mr_tx_message_num | |||
| R/WMC,0-0h | R-0h | 0h | R-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | mr_rx_ping | mr_tx_ping | mr_tx_snr | ||||
| R-0h | R-0h | R/W-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | mr_tx_valid | R/WMC,0 | 0h | This bit is used to indicate message data in registers 3.2308.11:8, 3.2309, 3.2310, 3.2311, and 3.2312 are valid and ready to be loaded. This bit shall self-clear when registers are loaded by the state machine. 1 = Message data in registers are valid 0 = Message data in registers are not valid |
| 14 | mr_tx_toggle | R | 0h | Toggle value to be transmitted with message. This bit is set by the state machine and cannot be overridden by the user. |
| 13 | mr_tx_received | 0h | This bit shall self clear on read. 1 = 1000BASE-T1 OAM message received by link partner 0 = 1000BASE-T1 OAM message not received by link partner | |
| 12 | mr_tx_received_toggle | R | 0h | Toggle value of message that was received by link partner |
| 11-8 | mr_tx_message_num | R/W | 0h | User-defined message number to send |
| 7-4 | RESERVED | R | 0h | Reserved |
| 3 | mr_rx_ping | R | 0h | Received PingTx value from latest good 1000BASE-T1 OAM frame received |
| 2 | mr_tx_ping | R/W | 0h | Ping value to send to link partner |
| 1-0 | mr_tx_snr | R | 0h | 00 = PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPI and send idles (used only when EEE is enabled). 10 = PHY SNR is marginal. 11 = PHY SNR is good. |
OAM_TX_MESSAGE_1 is shown in Figure 8-137 and described in Table 8-142.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_tx_message_15_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_tx_message_15_0 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_tx_message_15_0 | R/W | 0h | Message octet 1/0. LSB transmitted first. |
OAM_TX_MESSAGE_2 is shown in Figure 8-138 and described in Table 8-143.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_tx_message_31_16 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_tx_message_31_16 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_tx_message_31_16 | R/W | 0h | Message octet 3/2. LSB transmitted first. |
OAM_TX_MESSAGE_3 is shown in Figure 8-139 and described in Table 8-144.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_tx_message_47_32 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_tx_message_47_32 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_tx_message_47_32 | R/W | 0h | Message octet 5/4. LSB transmitted first. |
OAM_TX_MESSAGE_4 is shown in Figure 8-140 and described in Table 8-145.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_tx_message_63_48 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_tx_message_63_48 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_tx_message_63_48 | R/W | 0h | Message octet 7/6. LSB transmitted first. |
OAM_RECEIVE is shown in Figure 8-141 and described in Table 8-146.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_rx_lp_valid | mr_rx_lp_toggle | RESERVED | mr_rx_lp_message_num | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | mr_rx_lp_SNR | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | mr_rx_lp_valid | R | 0h | This bit is used to indicate message data in registers 3.2313.11:8, 3.2314, 3.2315, 3.2316, and 3.2317 are stored and ready to be read.
This bit shall self clear when register 3.2317 is read.
0h = Message data in registers are not valid 1h = Message data in registers are valid |
| 14 | mr_rx_lp_toggle | R | 0h | Toggle value received with message Note - 0x3 added in [15:12] to differentiate |
| 13-12 | RESERVED | R | 0h | Reserved |
| 11-8 | mr_rx_lp_message_num | R | 0h | Message number from link partner Note - 0x3 added in [15:12] to differentiate |
| 7-2 | RESERVED | R | 0h | Reserved |
| 1-0 | mr_rx_lp_SNR | R | 0h | 00 = Link partner link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain link partner SNR. Link partner requests local device to exit LPI and send idles (used only when EEE is enabled). 10 = Link partner SNR is marginal. 11 = Link partner SNR is good |
OAM_RX_MESSAGE_1 is shown in Figure 8-142 and described in Table 8-147.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_rx_lp_message_15_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_rx_lp_message_15_0 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_rx_lp_message_15_0 | R | 0h | Message octet 1/0. LSB transmitted first. |
OAM_RX_MESSAGE_2 is shown in Figure 8-143 and described in Table 8-148.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_rx_lp_message_31_16 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_rx_lp_message_31_16 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_rx_lp_message_31_16 | R | 0h | Message octet 3/2. LSB transmitted first. |
OAM_RX_MESSAGE_3 is shown in Figure 8-144 and described in Table 8-149.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_rx_lp_message_47_32 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_rx_lp_message_47_32 | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_rx_lp_message_47_32 | R | 0h | Message octet 5/4. LSB transmitted first. |
OAM_RX_MESSAGE_4 is shown in Figure 8-145 and described in Table 8-150.
Return to the Summary Table.
First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| mr_rx_lp_message_63_48 | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mr_rx_lp_message_63_48 | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | mr_rx_lp_message_63_48 | 0h | Message octet 7/6. LSB transmitted first. |
AN_CFG is shown in Figure 8-146 and described in Table 8-151.
Return to the Summary Table.
First nibble (0x7) in the register address is to indicated MMD register space. For register access, ignore the first nibble.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | mr_main_reset | ||||||
| R-0h | R/WSC-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | mr_main_reset | R/WSC | 0h | 1 = Reset link sync/autoneg Note - RW bit Note - Added 7 to [15:12] to differentiate |