ZHCSE90D September   2015  – September 2020 DLPC910

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Mirror Float
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_TYPE
        5. 7.3.7.5 DDC_Version(2:0)
        6. 7.3.7.6 DMD_IRQ
        7. 7.3.7.7 LED Indicators
          1. 7.3.7.7.1 VLED0
          2. 7.3.7.7.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

4 Revision History

Changes from Revision C (March 2020) to Revision D (September 2020)

  • Updated Description section for DDC_DCLK_(A,B,C,D)_DP(N,P), DDC_DIN_(A,B,C,D)(1-15)_DP(N,P), and DVALID_(A,B,C,D)_DP(N,P) from "100-Ω internal LVDS termination." to "100-Ω external LVDS termination required.Go
  • Updated I/O Type section for LOAD4_ENZ from LVCMOS33_I to LVCMOS25_I.Go
  • Updated I/O Type section for DMD_IRQ from LVCMOS33_O to LVCMOS25_O.Go
  • Corrected HBM and CDM values. Go
  • Corrected "...during which time RST_ACTIVE is asserted." to "...during which time RST_ACTIVE is NOT asserted."Go
  • Updated section name from "DMD Power Down" to "DMD Mirror Float". Removed outdated information about power down.Go
  • Removed "After PWR_FLOAT is asserted, a Mirror Clocking Pulse is issued, or a mirror Float operation is requested" Go
  • Updated I2C terminology to "primary" and "secondary" throughout section. Go
  • Updated performance plot for DLP6500 DMD (Figure 8-4) Go
  • Updated performance plot for DLP9000X/DLP9000XUV DMD (Figure 8-3)Go

Changes from Revision B (November 2016) to Revision C (March 2020)

  • 将标题从 DLPC910 数字控制器更改为 DLPC910 数字 DMD 控制器Go
  • 添加了新的 DLP9000XUV DMD 作为 DLPC910 支持的 DMD（多个位置）Go
  • Updated "DDC_IIC_x" signal names to "DDC_I2C_x" in multiple locationsGo
  • Added missing DLPC_DOUTBUSY pin to complete the listing of all 676 pins of DLPC910Go
  • Added missing unconnected pins to complete the listing of all 676 pins of DLPC910Go
  • Corrected signal name RESETZ to RESET_RSTZ Go
  • Added new DLP9000XUV DMD as DLPC910 supported device (DLP9000X/DLP9000XUV)Go
  • Deleted package code FLS from DMD callout for readability Go
  • Added section describing DDC_Version output pins Go
  • Corrected I2C version from 1.0-1995 to 1.0-1992. Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Fixed word "shorten" to "shortened" Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Combined Figure 8 and Figure 9 into new Figure 7-6 to incorporate Application Note/Tech Advisory dlpa092 (DLPC910 / DLPR910A - Continuous Row Command Operation). Go
  • Added DLP9000XUV to DMD Characteristics Table Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Changed "Connected DMD ID" to "Connected DMD TYPE" to match nomenclature of DMD_TYPE_[3:0] input pins Go
  • Added explanation that DDC_VERSION_(2:0) output values are mirrored in DESTOP_VERSION register.Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV to Figure 8-1 Go
  • Corrected signal name RESETZ to RESET_RSTZ in DLP9000X block diagram Go
  • Corrected signal name RESETZ to RESET_RSTZ in DLP6500 block diagram Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV Go
  • Added DLP9000XUV to Figure 9-1 - changed previous sentence to clarify one DMD per DLPC910/DLPR910.Go
  • Added DLP9000XUV link to Related Documentation section Go

Changes from Revision A (October 2015) to Revision B (November 2016)

Changes from Revision * (September 2015) to Revision A (October 2015)

  • 将器件状态从“产品预发布”更改为“量产数据”Go