ZHCSE90D September 2015 – September 2020 DLPC910
The DLPC910 detects the phase differences between the ½ speed clock (used in the device driving the LVDS data) and the internally generated ½ speed data clocks to select a clock phase for data capture. This is done by supplying a simple repeating pattern on all of the data inputs while the INIT_ACTIVE output of the DLPC910 is high/active. The details of the training pattern are described below.
Figure 7-1 shows a simple block diagram of the training pattern insertion logic.
The expected training pattern is 0100. In Figure 7-2, the data input to the 4:1 SERDES cells is captured on the rising edge of the ½ speed system clock. The output latency shown is based on the documentation for the Xilinx SERDES cells. Individual implementation may vary depending on the type of cells, technology, and design technique used.
In Xilinx FPGAs (due to the construction of the ISERDES and OSERDES cells) a pattern of 0010 needs to be applied to the output/transmitting SERDES cells data pins (D1 = 0, D2 = 0, D3 = 1, D4 = 0) in order to receive a result of 0100 (Q1 = 0, Q2 = 1, Q3 = 0, Q4 = 0) at the input/receiving SERDES cell.
The patterns should be applied on all of the data and DVALID pins. In this respect, the interface is treated as a 17 bit interface with DVALID being the 17th data bit. The receiving logic in the DLPC910 adjusts the clock phase until the correct pattern is seen at the inputs. This allows DLPC910 to correctly select a clock phase for data capture and will contribute to a more robust interface. It is important that the training pattern is applied to the DVALID and data inputs of the DLPC910 before reset to the device is de-asserted, as training commences immediately on the de-assertion of reset. The INIT_ACTIVE signal is asserted while the device is held in reset in order to help facilitate this behavior.