ZHCSE90D September   2015  – September 2020 DLPC910

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Mirror Float
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_TYPE
        5. 7.3.7.5 DDC_Version(2:0)
        6. 7.3.7.6 DMD_IRQ
        7. 7.3.7.7 LED Indicators
          1. 7.3.7.7.1 VLED0
          2. 7.3.7.7.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.4.2 Block Mode Operation

The DMD mirrors and corresponding SRAM pixels are organized into blocks and each block is broken into rows per BLK as described in Table 7-11. Mirror blocks are addressed for either the Mirror Clocking Pulse or Block Clear functions by asserting block control signals at the start of each row data load. RST2BLKZ, BLKMD and BLKAD are used as shown in Table 7-12 to designate which mirror block(s) is to be issued a MCP or a Block Clear. Refer to Related Documentation for the DMD datasheet regarding block location information.

  • The clear operation sets all of the SRAM pixels in the designated block to logic zero during the current row cycle.
  • It is possible to issue a MCP to a block while loading a different block.
  • It is not possible to clear a block while writing to a different block.
  • It is not necessary to clear a block if it is going to be reloaded with new data (just like a normal memory cell).
  • It is recommended that RST2BLKZ, COMP, and NS_FLIP be set to one value and not adjusted during normal system operation.
  • A change in RST2BLKZ is not immediately effective and will require more than one row load cycle to complete.

Note:

RST2BLK needs to be kept low during initialization for proper setup of the system. Dynamic changes to RST2BLK during normal operation are not recommended.

Table 7-11 DMD Characteristics
TYPE COLS ROWS BLKS ROWS PER BLK CLKS PER ROW #DATA IN Required Output LVDS Buses Required Input LVDS Buses
DLP9000X - 0.9 WQXGA Type A 2560 1600 16 100 20 64 A, B, C, and D A, B, C, and D
DLP9000XUV - 0.9 WQXGA Type A 2560 1600 16 100 20 64 A, B, C, and D A, B, C, and D
DLP6500 - 0.65 1080p Type A and S600 1920 1080 15 72 32 32 A and B(1)
or
C and D		 A and B
(1) By default data and serial control outputs are active on buses A and B. Refer to Section 7.5.1.9 to activate data and serial control outputs on buses C and D.
Table 7-12 Block Operations
RST2BKLZBLKMD_1BLKMD_2BLKAD_3BLKAD_2BLKAD_1BLKAD_0OPERATION
X00XXXXNone
X010000Clear block 00
X010001Clear block 01
X010010Clear block 02
X010011Clear block 03
X010100Clear block 04
X010101Clear block 05
X010110Clear block 06
X010111Clear block 07
X011000Clear block 08
X011001Clear block 09
X011010Clear block 10
X011011Clear block 11
X011100Clear block 12
X011101Clear block 13
X011110Clear block 14
X011111Clear block 15 (1)
X100000Reset block 00
X100001Reset block 01
X100010Reset block 02
X100011Reset block 03
X100100Reset block 04
X100101Reset block 05
X100110Reset block 06
X100111Reset block 07
X101000Reset block 08
X101001Reset block 09
X101010Reset block 10
X101011Reset block 11
X101100Reset block 12
X101101Reset block 13
X101110Reset block 14
X101111Reset block 15 (1)
0110000Reset blocks 00-01
0110001Reset blocks 02-03
0110010Reset blocks 04-05
0110011Reset blocks 06-07
0110100Reset blocks 08-09
0110101Reset blocks 10-11
0110110Reset blocks 12-13
0110111Reset blocks 14-15
111000XReset blocks 00-03
111001XReset blocks 04-07
111010XReset blocks 08-11
111011XReset blocks 12-15
X1110XXReset blocks 00-15
X1111XXFloat blocks 00-15
(1) Not applicable on DLP6500.