ZHCSE90D September   2015  – September 2020 DLPC910

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Mirror Float
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_TYPE
        5. 7.3.7.5 DDC_Version(2:0)
        6. 7.3.7.6 DMD_IRQ
        7. 7.3.7.7 LED Indicators
          1. 7.3.7.7.1 VLED0
          2. 7.3.7.7.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7.4.4 Mirror Clocking Pulse

A Mirror Clocking Pulse (MCP) sequence begins by asserting BLKMD and BLKAD for a single, dual, quad, or global block operation as defined in Table 7-12. A MCP causes a reset on the block(s), and the data stored in the block(s) takes effect on the mirrors of the DMD. Shortly after a MCP has been issued, RST_ACTIVE goes high for approximately 4 μs, indicating a MCP operation is in progress. During this time, no additional MCPs may be initiated until RST_ACTIVE returns low. RST_ACTIVE does not return to low unless continuous no-op or data loading row cycles are issued. A typical single block load phased sequence in which consecutive DMD blocks are loaded is illustrated in Figure 7-8. A MCP time is identical for single, dual, quad or global block operations.

Note that it may take longer to complete a MCP on a block than it does to load a block. The block load time may be calculated as:

Block Load Time = Clock Period × number CLKS per ROW × number ROWS per BLK
Table 7-13 DMD Block Load Time
DMDMINIMUM BLOCK LOAD TIMEDCLKIN (MHz)
DLP9000X4.167 µsec480
DLP9000XUV4.167 µsec480
DLP65005.76 µsec400

For any case which involves sending a MCP or a Block Clear without data loading, the customer interface must send no-op row cycles. This can be accomplished by asserting DVALID, while holding ROWMD at 00 and BLKMD at 00 for the number of clocks per row in the DMD, as in Figure 7-7. Refer to Table 7-11 to obtain the number of clocks per row. Following the loading of all rows in a block or the entire DMD, at least one no-op row cycle must be completed to initiate the MCP. If the MCP is asserted prior to loading all rows in a block or the entire DMD, rows which were not updated will show old data. Additional MCP operations may not be initiated until RST_ACTIVE is low. Block Clear operations for the DMD must be followed by two consecutive no-op row cycle commands.

To obtain full utilization of the DMD bandwidth, load four blocks and then issue a MCP to the four blocks concurrently by setting RST2BLKZ to 1 and BLKMD to 11 with the appropriate address in BLKAD. This is illustrated in Figure 7-10.

It is possible to load other blocks while the block(s) previously issued a MCP is settling. This is illustrated in Figure 7-9 and Figure 7-10, where blocks are reloaded while the mirror setting time is occurring. It is also possible to load other blocks while previously loaded block(s) have an outstanding RST_ACTIVE. This is illustrated in Figure 7-10, where block 0 is loaded while RST_ACTIVE is asserted for blocks 12-15.

Note:

While RST_ACTIVE is high for 4 μs, the data for the block(s) being issued a MCP should not be changed to allow the mirrors to become stable. The RST_ACTIVE does not include the mirror settling period. A short delay of 6 μs should be introduced during the last block(s) that is issued a MCP. The mirror settling time is illustrated in Figure 7-8, Figure 7-9, Figure 7-10, and Figure 7-11, where the customer interface introduces a delay on the last block(s) that were issued a MCP to allow the mirrors to become stable.

Figure 7-8, Figure 7-9, Figure 7-10, and Figure 7-11 all show an exposure period. Once the customer interface has issued all required MCPs and the proper mirror settling time has been applied, the customer interface may pulse an illumination source onto the DMD during this period. The exposure period is user adjustable; however, increasing the exposure period decreases the pattern rate. Refer to Application Curves regarding exposure period.

Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, and Figure 7-11 show timing for the DLP9000X/DLP9000XUV. Refer to Table 7-11 to obtain the number of reset blocks and clocks per row for the DLP6500 DMD.

GUID-B2C0C141-B305-40D1-A8C4-9F13E8312329-low.gifFigure 7-7 DMD No-op Row Cycle
GUID-98AAA9BB-A030-4638-AB27-B2597ECFC7E1-low.gifFigure 7-8 Single Block Load Phased Sequence
GUID-EB329475-3A36-475A-A026-D339C39AFEA9-low.gifFigure 7-9 Dual Block Load Phased Sequence
GUID-BD689ECA-455D-4C6C-81DE-F1212ECF0740-low.gifFigure 7-10 Quad Block Load Phased Sequence
GUID-72F42262-186A-4EA1-8809-BEE415428AAD-low.gifFigure 7-11 Full DMD Global Load Sequence

Note: After a MCP or Block Clear command is given, RST_ACTIVE may not be asserted until up to 60 ns (depending on the clock frequency) after the command. While RST_ACTIVE is asserted, no other command should be given.