ZHCSHH9D January   2017  – August 2021 DLPC3437

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 Parallel Interface Data Transfer Format
      2. 7.3.2 Device Start-Up
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast PARK Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

4 Revision History

Changes from Revision C (June 2019) to Revision D (August 2021)

  • 总数据表格式和订购更新Go
  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将提到 I2C 或 SPI 的旧术语实例全局更改为初级和次级。Go
  • Deleted mention of mirror parking time from PARKZ pin description and moved to a specification tableGo
  • Changed JTAG pin names from Reserved to proper names Go
  • Deleted support for adjustable DATAEN_CMD polarity Go
  • Deleted support for adjusting PCLK capture edge in software Go
  • Added DSI pin informationGo
  • Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use GPIO_10 (RC_CHARGE) instead of CMP_PWM Go
  • Deleted support for CMP_PWMGo
  • Deleted mention of unsupported light sensor on GPIO_13 and GPIO_12 Go
  • Deleted reference of the LS_PWR circuit being used for the light sensorGo
  • Deleted mention of the unsupported LABB output sample and hold sensor control signalGo
  • Clarified GPIO_03 - GPIO_01 pins are required to be used as a SPI1 portGo
  • Deleted unneeded VCC_INTF and VCC_FLSH absolute maximum values Go
  • Changed Updated VDDLP12 information Go
  • Changed incorrect pin tolerance Go
  • Changed and fixed incorrect test conditions for current drive strengthsGo
  • Deleted redundant ǀVODǀ specification which is referenced in later sectionsGo
  • Added minimum and maximum values for VOH for I/O type 4Go
  • Added minimum and maximum values for VOL for I/O type 4Go
  • Deleted incorrect reference to 2.5V, 24mA drive Go
  • Deleted incorrect steady-state common mode voltage reference Go
  • Changed high voltage tolerant I/O note to only refer to the I2C buffer and changed VCC to VCC_INTF.Go
  • Added |VOD| minimum and maximum values, and changed the typical value.Go
  • Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Corrected the name of the DMD Low-Speed signals from inputs to outputs. Go
  • Deleted VOH(DC) maximum and VOL(DC) minimum values. Go
  • Added note about DMD input specs being met if a proper series termination resistor is used Go
  • Deleted reference of selecting unsupported oscillator frequency Go
  • Corrected system oscillator clock period to match clock frequency Go
  • Changed pulse duration percent spec from a maximum to a minimum Go
  • Added condition for VDD rise time Go
  • Changed the minimum flash SPI_CLK frequencyGo
  • Corrected flash interface clock period to match clock frequency Go
  • Changed DMD HS Clock switching rate from maximum to nominal and added accompanying clock specification Go
  • Added the Section 6.18 section to clarify chipset support requirementsGo
  • Added information that the parallel interface isn't ready to accept data until the auto-initialization process is completedGo
  • Changed how the 500 ms startup time is described Go
  • Changed device markings image and definitions Go

Changes from Revision B (January 2018) to Revision C (June 2019)

  • Changed mirror parking time from "500 μs" to "20 ms" for PARKZ description in Pin Functions tableGo
  • Added Section 7.3.7 Go