ZHCSHA4B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Daisy-Chain Mode

When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several DACs, the SDO pin may be used to daisy-chain several devices together.

In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. These data are clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the DIN input on the next DAC in the chain, a multi-DAC interface is constructed. 16 clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must be equal to (16 x N), where N is the total number of devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action prevents any further data from being clocked into the input shift register. The contents in the shift registers are transferred into the relevant input registers on the rising edge of the CS signal.

A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers, and all analog outputs update simultaneously.