ZHCSHA4B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.8 Typical Characteristics: VDD = +5 V

At TA = +25°C, VREFH = +5 V, VREFL = 0 V, and Gain = 1X Mode, unless otherwise noted.

DAC8881 tc_5v_25c_inl_bas422.gifFigure 4. Linearity Error vs Digital Input Code
DAC8881 tc_5v_40c_inl_bas422.gifFigure 6. Linearity Error vs Digital Input Code
DAC8881 tc_5v_105c_inl_bas422.gifFigure 8. Linearity Error vs Digital Input Code
DAC8881 tc_5v_inl-tmp_bas422.gifFigure 10. Linearity Error vs Temperature
DAC8881 tc_5v_inl-tmp_2x_bas422.gifFigure 12. Linearity Error vs Temperature
(Gain = 2X Mode)
DAC8881 tc_5v_inl-vs_bas422.gifFigure 14. Linearity Error vs Supply Voltage
DAC8881 tc_5v_inl-vref_bas422.gifFigure 16. Linearity Error vs Reference Voltage
DAC8881 tc_5v_end-tmp_bas422.gifFigure 18. Endpoint Error vs Temperature
DAC8881 tc_5v_is-code_bas422.gifFigure 20. AVDD Supply Current vs Digital Input Code
DAC8881 tc_5v_is-tmp_bas422.gifFigure 22. AVDD Supply Current vs Temperature
DAC8881 tc_5v_iref-code_bas422.gifFigure 24. Reference Current vs Digital Input Code
DAC8881 tc_5v_vo-dcc_bas422.gifFigure 26. Output Voltage vs Drive Current Capability
DAC8881 tc_5v_vo-dcc_agnd_bas422.gifFigure 28. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
DAC8881 tc_5v_time_0-f_bas422.gifFigure 30. Large Signal Settling Time
DAC8881 tc_5v_time_1-f_bas422.gifFigure 32. Large Signal Settling Time
DAC8881 tc_5v_time_0-f_2x_bas422.gifFigure 34. Large Signal Settling Time (Gain = 2X Mode)
DAC8881 tc_5v_time_1-f_2x_bas422.gifFigure 36. Large Signal Settling Time (Gain = 2X Mode)
DAC8881 tc_5v_glch_7-8_5v_bas422.gifFigure 38. Major Carry Glitch
DAC8881 tc_5v_glch_7-8_25v_bas422.gifFigure 40. Major Carry Glitch
DAC8881 tc_5v_noise-frq_bas422.gifFigure 42. Output Noise Density vs Frequency
DAC8881 tc_5v_25c_dnl_bas422.gifFigure 5. Differential Linearity Error vs Digital Input Code
DAC8881 tc_5v_40c_dnl_bas422.gifFigure 7. Differential Linearity Error vs Digital Input Code
DAC8881 tc_5v_105c_dnl_bas422.gifFigure 9. Differential Lineary Error vs Digital Input Code
DAC8881 tc_5v_dnl-tmp_bas422.gifFigure 11. Differential Linearity Error vs Temperature
DAC8881 tc_5v_dnl-tmp_2x_bas422.gifFigure 13. Differential Linearity Error vs Temperature
(Gain = 2X Mode)
DAC8881 tc_5v_dnl-vs_bas422.gifFigure 15. Differential Linearity Error vs Supply Voltage
DAC8881 tc_5v_dnl-vref_bas422.gifFigure 17. Differential Linearity Error vs Reference Voltage
DAC8881 tc_5v_end-tmp_2x_bas422.gifFigure 19. Endpoint Error vs Temperature
(Gain = 2X Mode)
DAC8881 tc_5v_is-code_2x_bas422.gifFigure 21. AVDD Supply Current vs Digital Input Code
(Gain = 2X Mode)
DAC8881 tc_5v_ipd-tmp_bas422.gifFigure 23. AVDD Power-Down Current vs Temperature
DAC8881 tc_5v_iref-code_2x_bas422.gifFigure 25. Reference Current vs Digital Input Code
(Gain = 2X Mode)
DAC8881 tc_5v_vo-dcc_avdd_bas422.gifFigure 27. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
DAC8881 tc_5v_iovdd-logic_bas422.gifFigure 29. IOVDD Supply Current vs Logic Input Voltage
DAC8881 tc_5v_time_f-0_bas422.gifFigure 31. Large Signal Settling Time
DAC8881 tc_5v_time_f-1_bas422.gifFigure 33. Large Signal Settling Time
DAC8881 tc_5v_time_f-0_2x_bas422.gifFigure 35. Large Signal Settling Time (Gain = 2X Ml)
DAC8881 tc_5v_time_f-1_2x_bas422.gifFigure 37. Large Signal Settling Time (Gain = 2X Mode)
DAC8881 tc_5v_glch_8-7_5v_bas422.gifFigure 39. Major Carry Glitch
DAC8881 tc_5v_glch_8-7_25v_bas422.gifFigure 41. Major Carry Glitch
DAC8881 tc_5v_lfo_noise_bas422.gif
Figure 43. Low-Frequency Output Noise (0.1Hz to 10Hz)