ZHCSHA4B July 2007 – January 2018 DAC8881
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
6.8 Typical Characteristics: VDD = +5 V
At TA = +25°C, VREFH = +5 V, VREFL = 0 V, and Gain = 1X Mode, unless otherwise noted.
Figure 4. Linearity Error vs Digital Input Code
Figure 6. Linearity Error vs Digital Input Code
Figure 8. Linearity Error vs Digital Input Code
Figure 10. Linearity Error vs Temperature
Figure 12. Linearity Error vs Temperature
(Gain = 2X Mode)
Figure 14. Linearity Error vs Supply Voltage
Figure 16. Linearity Error vs Reference Voltage
Figure 18. Endpoint Error vs Temperature
Figure 20. AVDD Supply Current vs Digital Input Code
Figure 22. AVDD Supply Current vs Temperature
Figure 24. Reference Current vs Digital Input Code
Figure 26. Output Voltage vs Drive Current Capability
Figure 28. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
Figure 30. Large Signal Settling Time
Figure 32. Large Signal Settling Time
Figure 34. Large Signal Settling Time (Gain = 2X Mode)
Figure 36. Large Signal Settling Time (Gain = 2X Mode)
Figure 38. Major Carry Glitch
Figure 40. Major Carry Glitch
Figure 42. Output Noise Density vs Frequency
Figure 5. Differential Linearity Error vs Digital Input Code
Figure 7. Differential Linearity Error vs Digital Input Code
Figure 9. Differential Lineary Error vs Digital Input Code
Figure 11. Differential Linearity Error vs Temperature
Figure 13. Differential Linearity Error vs Temperature
(Gain = 2X Mode)
Figure 15. Differential Linearity Error vs Supply Voltage
Figure 17. Differential Linearity Error vs Reference Voltage
Figure 19. Endpoint Error vs Temperature
(Gain = 2X Mode)
Figure 21. AVDD Supply Current vs Digital Input Code
(Gain = 2X Mode)
Figure 23. AVDD Power-Down Current vs Temperature
Figure 25. Reference Current vs Digital Input Code
(Gain = 2X Mode)
Figure 27. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
Figure 29. IOVDD Supply Current vs Logic Input Voltage
Figure 31. Large Signal Settling Time
Figure 33. Large Signal Settling Time
Figure 35. Large Signal Settling Time (Gain = 2X Ml)
Figure 37. Large Signal Settling Time (Gain = 2X Mode)
Figure 39. Major Carry Glitch
Figure 41. Major Carry Glitch
