ZHCSHA4B July 2007 – January 2018 DAC8881
PRODUCTION DATA.
Data are loaded into the device as a 16-bit word under the control of the serial clock input, SCLK. The timing diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while CS is low. To start the serial data transfer, CS should be taken low, observing the minimum CS falling edge to SCLK rising edge setup time, t2. After CS goes low, serial data are clocked into the device input shift register on the rising edges of SCLK for 16 or more clock pulses. If a frame contains less than 16 bits of data, the frame is invalid. Invalid data are not written into the input register and DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than 16 bits of data are transmitted in one frame, the last 16 bits are written into the shift register and DAC. CS may be taken high after the rising edge of the 16th SCLK pulse, observing the minimum SCLK rising edge to CS rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and DAC output can be updated by taking the LDAC pin low.