ZHCSJ19D November   2018  – February 2020 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
      2.      使用 DACx0501 进行失调电压修整
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements : SPI Mode
    7. 7.7  Timing Requirements : I2C Standard Mode
    8. 7.8  Timing Requirements : I2C Fast Mode
    9. 7.9  Timing Requirements : I2C Fast-Mode Plus
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 DACx0501 I2C Update Sequence
            1. 8.5.1.2.2.1 DACx0501 Address Byte
            2. 8.5.1.2.2.2 DACx0501 Command Byte
            3. 8.5.1.2.2.3 DACx0501 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 DACx0501 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 NOOP Register (offset = 0h) [reset = 0000h]
        1. Table 8. NOOP Register Field Descriptions
      2. 8.6.2 DEVID Register (offset = 1h)
        1. Table 9. DEVID Register Field Descriptions
      3. 8.6.3 SYNC Register (offset = 2h) [reset = 0000h]
        1. Table 10. SYNC Register Field Descriptions
      4. 8.6.4 CONFIG Register (offset = 3h) [reset = 0000h]
        1. Table 11. CONFIG Register Field Descriptions
      5. 8.6.5 GAIN Register (offset = 4h) [reset = 0001h]
        1. Table 12. GAIN Register Field Descriptions
      6. 8.6.6 TRIGGER Register (offset = 5h) [reset = 0000h]
        1. Table 13. TRIGGER Register Field Descriptions
      7. 8.6.7 STATUS Register (offset = 7h) [reset = 0000h]
        1. Table 14. STATUS Register Field Descriptions
      8. 8.6.8 DAC Register (offset = 8h) [reset = 0000h for DACx0501Z or reset = 8000h for DACx0501M]
        1. Table 15. DAC Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 16 位性能:1LSB INL 和 DNL(最大值)
  • 低毛刺脉冲能量:4nV-s
  • 宽电源电压范围:2.7V 至 5.5V
  • 缓冲输出范围:5V、2.5V 或 1.25V
  • 极低功耗:1mA (5.5V)
  • 集成 5ppm/˚C(最大值)、2.5V 精密基准
  • 引脚可选串行接口:
    • 3 线制,兼容 SPI,高达 50MHz
    • 两线制,兼容 I2C
  • 上电复位:零电平或中间电平
  • VDD = 5.5V 时的 VIH 为 1.62V
  • 温度范围:–40˚C 至 +125˚C
  • 封装:小型 8 引脚 WSON 和 10 引脚 VSSOP